Circuit and method for optimization with digital adder, analog adder, and multiplier

A multiplier-adder, comprising a circuit, the circuit comprising:

• a multiplier comprising a plurality of word lines, a plurality of bit lines, and a plurality of storage units;
• and
• a digital addition circuit and an analog addition circuit coupled to the multiplier, wherein:
• the digital addition circuit is configured to perform bitwise digital accumulation on bits that belong to a first bit position range and that are in a plurality of groups of partial products, wherein the plurality of groups of partial products are obtained by multiplying a plurality of first values by a plurality of second values, the first bit position range refers to S bit positions of a product value of one of the first values and one of the second values, S is a positive integer, and the product value is obtained by performing bitwise accumulation after a group of partial products are shifted;
• and
• the analog addition circuit is configured to perform bitwise analog accumulation on analog parameters corresponding to values of bits that belong to a second bit position range and that are in the plurality of groups of partial products, wherein the second bit position range refers to T bit positions that are of the product value and that do not overlap the first bit position range, T is a positive integer, and S+T is less than or equal to a quantity of bit positions of the product value.

A circuit optimization method, applied to a multiplier-adder comprising a circuit comprising a digital addition circuit and an analog addition circuit, wherein:

• the digital addition circuit is configured to perform bitwise digital accumulation on bits that belong to a first bit position range and that are in a plurality of groups of partial products, wherein the plurality of groups of partial products are obtained by multiplying a plurality of first values by a plurality of second values, the first bit position range refers to S bit positions of a product value of one of the first values and one of the second values, S is a positive integer, and the product value is obtained by performing bitwise accumulation after a group of partial products are shifted;
• and
• the analog addition circuit is configured to perform bitwise analog accumulation on analog parameters corresponding to values of bits that belong to a second bit position range and that are in the plurality of groups of partial products, the second bit position range refers to T bit positions that are of the product value and that do not overlap the first bit position range, T is a positive integer, and S+T is less than or equal to a quantity of bit positions of the product value;
• and
• the circuit optimization method comprises:
• calculating power consumption of the multiplier-adder in each data pair, wherein each data pair comprises a first bit position range in which digital accumulation is performed by the multiplier-adder and a second bit position range in which analog accumulation is performed by the multiplier-adder;
• and
• generating an optimized multiplier-adder based on an optimal data pair, wherein the optimal data pair is the first bit position range and the second bit position range when power consumption of the multiplier-adder is at a lowest level.