US 5,319,755 A · Integrated circuit I/O using high performance bus interface

Abstract

An apparatus for storing and retrieving data is described. The apparatus includes a circuitry for initiating data transmission, a first memory, a second memory, and a multiline bus for transferring control information, addresses, and the data. The control information includes information for selecting one of the first and second memories without using any separate memory select line. Configuration circuitry is provided for assigning a first identification value to the first memory and a second identification value to the second memory. The configuration circuitry includes a first reset line for coupling the circuitry for initiating data transmission to the first memory, a second reset line for coupling the first memory to the second memory, a first identification register for the first memory, a second identification register for the second memory, circuitry for generating a first reset signal and a second reset signal and for sending the first and second reset signals to the first identification register, circuitry for propagating the first and second reset signals from the first identification register to the second identification register, circuitry for resetting the first and second identification registers in response to the first reset signal, and circuitry for setting the first identification register to the first identification value and the second identification register to the second identification value in response to the second reset signal.

An apparatus for storing and retrieving data, wherein the apparatus comprises:

(A) a first memory;
(B) a second memory;
(C) a multiline bus for coupling the first and second memories and for carrying control information, addresses, and the data, wherein the multiline bus has a total number of lines less than a total number of bits in any single address, wherein the control information includes information for selecting one of the first and second memories without using any separate memory select line;
(D) a multiline transceiver bus;
(E) means for initiating data transmission coupled to the multiline transceiver bus;
(F) a transceiver for coupling the multiline transceiver bus to the multiline bus, for coupling the means for initiating data transmission to the first and second memories, and for carrying the control information, addresses, and the data, wherein the multiline transceiver bus has a total number of lines less than a total number of bits in any single address, wherein the control information includes information for selecting one of the first and second memories without using any separate memory select line;
(G) configuration means for assigning a first identification value to the first memory and a second identification value to the second memory, wherein the configuration means further comprises:
(i) a first reset line for coupling the means for initiating data transmission to the first memory;
(ii) a second reset line for coupling the first memory to the second memory;
(iii) a first identification register for the first memory, wherein the first identification register is coupled to the first reset line and the multiline bus;
(iv) a second identification register for the second memory, wherein the second identification register is coupled to the second reset line and the multiline bus;
(v) means for generating a first reset signal and a second reset signal and for sending the first reset signal and the second reset signal to the first identification register of the first memory, wherein the generating means is coupled to the first reset line and the multiline bus, wherein the generating means also generates the first identification value and the second identification value;
(vi) means for propagating the first reset signal and the second reset signal from the first identification register of the first memory to the second identification register of the second memory, wherein the propagating means is coupled to the first identification register and the second reset line;
(vii) means in each of the first and second identification registers for resetting the first and second identification registers in response to the first reset signal, wherein the resetting means receives the first reset signal in the first identification register from the first reset line and in the second identified register from the second reset line;
(viii) means in each of the first and second identification registers for setting the first identification register to the first identification value and the second identification register to the second identification value in response to the second reset signal, wherein the setting means causes the first identification register to receive the first identification value from the generating means (1) the first reset line or (2) the multiline bus when the first identification register receives the second reset signal via the first reset line, wherein the setting means causes the second identification register to receive the second identification value from the generating means via (1) the first and second reset lines or (2) the multiline bus when the second identification register receives the second reset signal via the second reset line.

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Integrated circuit I/O using high performance bus interface

Life of this patent

Integrated circuit I/O using high performance bus interface

Life of this patent

Abstract

Claims59