Configurable data protection circuitry for memory devices

A method, comprising:

• receiving, by a controller, data corresponding to a number of codewords from a plurality of memory channels, wherein each memory channel is coupled to a number of memory devices, and wherein each memory device of the number of memory devices:
• is configured to store data corresponding to one or more of the number of codewords;
• and
• has a particular operating mode corresponding to its input/output (I/O) width;
• and
• operating data protection circuitry of the controller configured to:
• accommodate a first codeword configuration of the number of codewords;
• and
• accommodate a second codeword configuration of the number of codewords that is different from the first codeword configuration, wherein:
• a first codeword comprises a plurality of first symbols and a second codeword comprises a plurality of second symbols;
• and
• each respective channel simultaneously transfers a first symbol to the controller to form the first codeword and transfers a second symbol to the controller to form the second codeword.

An apparatus, comprising:

• a memory controller configured to map input/output (I/O) pins to receive codewords from a plurality of memory devices;
• a plurality of channels coupled to the memory controller and configured to transfer the codewords from the plurality of memory devices to the memory controller;
• and
• a plurality of multiplexors configured to switch between a plurality of signaling paths for the codewords, wherein switching between the plurality of signaling paths facilitates different modes of chip kill circuitry in the memory controller.

An apparatus, comprising:

• a memory controller configured to map input/output (I/O) pins to receive codewords from a plurality of memory devices;
• a plurality of channels coupled to the memory controller and configured to transfer the codewords from the plurality of memory devices to the memory controller;
• and
• a plurality of multiplexors configured to switch between a plurality of signaling paths for the codewords, wherein:
• a first codeword comprises a plurality of first symbols and a second codeword comprises a plurality of second symbols;
• and
• each respective channel transfers a first symbol to the memory controller to form the first codeword, transfers a second symbol to the memory controller to form the second codeword, transfers a third signal to the memory controller to form a third codeword, and transfers a fourth symbol to the memory controller to form a fourth codeword.