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US 6,172,918 B2Granted
Semiconductor memory device allowing high-speed operation of internal data buses
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHideto Hidaka
Life of this patent
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Abstract
A current mirror-type load circuit is provided for a global data line pair. A read gate amplifier used as a block select gate for each of the local data line pairs. A read gate amplifier includes a MOS transistor having its gate connected to a corresponding local data line. A data write driver writes the logic-inverted data of the write data upon equalization after the data write operation. A high-speed access becomes possible by reducing the time required for reading of data and by reducing the write recovery time.
Claims27
A semiconductor memory device, comprising:
- a plurality of memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns, and arranged in alignment at least in a column-direction;
- a plurality of local data line pairs provided corresponding to said memory blocks, each of said plurality of local data line pairs being coupled to a selected memory cell in a corresponding memory block;
- a global data line pair provided in common to the memory blocks arranged in alignment in the column-direction;
- a plurality of read gate amplifiers each provided between each of said plurality of local data line pairs and said global data line pair, for transmitting, when selected, a signal of a corresponding local data line pair to said global data line pair, with said corresponding local data line pair and said global data line pair being electrically isolated;
- and
- a current supply load circuit coupled to said global data line pair for supplying a current of a same magnitude to each data line of said global data line pair.
3 more elements
A semiconductor memory device, comprising:
- a plurality of memory cells;
- an internal data line pair for transmitting write data to a selected memory cell of said plurality of memory cells;
- an equalizing circuit coupled to said internal data line pair for equalizing voltages of said internal data line pair in response to an equalizing instruction signal;
- and
- a write circuit for generating an internal write data according to an externally applied write data and transmitting the internal write data to said internal data line pair, said write circuit generating a logic-inverted data of said internal write data in response to activation of said equalizing instruction signal and transmitting the logic-inverted data to said internal data line pair.
2 more elements
A semiconductor memory device, comprising:
- a plurality of array blocks each including a plurality of memory cells arranged in a matrix of rows and columns and a plurality of bit line pairs arranged corresponding to the columns and connecting memory cells of corresponding columns;
- a plurality of local data line pairs arranged extending in a row-direction and corresponding to said plurality of array blocks;
- a plurality of column select gates disposed corresponding to said plurality of bit line pairs in each of said plurality of array blocks, for electrically connecting a bit line pair corresponding to a selected column to a corresponding local data line pair in response to a column select signal;
- a global data line pair extending in a column-direction and arranged in common to array blocks, of said plurality of array blocks, disposed in alignment in the column-direction;
- a plurality of read gates each provided between each of said local data line pairs and said global data line pair, each of said plurality of read gates including a select gate pair made conductive in response to a block select signal activated according to an address signal in a data read mode, and a differential gate pair including an insulated gate field effect transistor receiving a signal on a corresponding local data line pair at a gate thereof, said differential gate pair and said select gate pair being connected in series between said global data line pair and a reference voltage node;
- and
- a current mirror-type load circuit coupled to said global data line pair, for supplying, when activated, current to said global data line pair.
4 more elements
A semiconductor memory device comprising:
- a plurality of memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns;
- a plurality of local data line pairs provided corresponding to said plurality of memory blocks, each for communicating data with a selected memory cell in a corresponding memory block;
- a global data line pair provided in common to the memory blocks;
- a plurality of read gate amplifiers each provided between each of said plurality of local data line pairs and said global data line pair, for transmitting, when selected, a signal of a corresponding local data line pair to said global data line pair;
- and
- a current supply load circuit coupled to said global data line pair for supplying a current to each data line of said global data line pair.
3 more elements
Dependencies are inferred from the claim text.