Memory circuitry having bus interface for receiving information in packets and access time registers

An interface circuitry for accessing a semiconductor memory circuit, comprising:

• (A) receiver circuitry coupled to a multiline bus for receiving data, addresses, and control information that are multiplexed and transmitted in a form of packets via the multiline bus, wherein the multiline bus has a total number of lines less than a total number of bits in any single address, wherein the computer system includes a plurality of semiconductor circuits, including the memory circuit, wherein all circuitry of the interfacing circuitry resides inside the memory circuit;
• (B) decoder circuitry coupled to the receiver circuitry for decoding the packets received in the receiver circuitry to identify the data, addresses, and control information;
• (C) control logic circuitry coupled to the decoder circuitry for controlling device operation of the memory circuit in accordance with the data, addresses, and control information received from the multiline bus and for transmitting reply information through the multiline bus in response to the data, addresses, and control information received, the reply information generated in response to accessing the memory circuit;
• and;
• (D) register circuitry coupled to the control logic circuitry for storing a first value corresponding to a first predetermined time period during which the interfacing circuitry must wait before transmitting the reply information through the multiline bus, wherein the register circuitry applies the first value to the control logic circuitry to cause the control logic circuitry to wait for the first predetermined time period before accessing the multiline bus for transmitting the reply information, wherein the register circuitry allows modification of the first value by the control logic circuitry under control of the data, addresses, and control information received from the multiline bus.