Apparatus for synchronously generating clock signals in a data processing system

An apparatus for synchronously generating a first clock signal for a first semiconductor circuitry of a data processing system and a second clock signal for a second semiconductor circuitry of the data processing system, wherein the apparatus comprises:

• (A) clock generating means for generating a global clock signal;
• (B) transmission line means for transferring the global clock signal from a first end to a second end, wherein the transmission line means includes (1) the first end coupled to the clock generating means to receive the global clock signal and (2) the second end, wherein the transmission line means includes a midpoint between the first end and the second end;
• (C) first clock signal generation means in the first semiconductor circuitry for generating the first clock signal for the first semiconductor circuitry, wherein the first clock signal generation means is coupled at (1) a first point of the transmission line means for receiving the global clock signal and (2) a second point of the transmission line means for receiving the global clock signal, wherein the first point is between the first end and the midpoint, wherein the second point is between the midpoint and the second end, wherein a line length from the midpoint to the first point is equal to the line length from the midpoint to the second point, wherein the first clock signal generation means at the first point receives the global clock signal with a first propagation delay of the transmission line means from the first end to the first point, wherein the first clock signal generation means at the second point receives the global clock signal with a second propagation delay of the transmission line means from the first end to the second point, wherein the first clock signal generation means generates the first clock signal at a first timing that is halfway between the global clock signal with the first propagation delay and the global clock signal with the second propagation delay, wherein the first timing of the first clock signal coincides with the global clock signal with a midpoint propagation delay of the transmission line means from the first end to the midpoint;
• (D) second clock signal generation means in the second semiconductor circuitry for generating the second clock signal for the second semiconductor circuitry, wherein the second clock signal generation means is coupled at (1) a third point of the transmission line means for receiving the global clock signal and (2) a fourth point of the transmission line means for receiving the global clock signal, wherein the third point is between the first end and the midpoint, wherein the fourth point is between the midpoint and the second end, wherein the line length from the midpoint to the third point is equal to the line length from the midpoint to the fourth point, wherein the second clock signal generation means at the third point receives the global clock signal with a third propagation delay of the transmission line means from the first end to the third point, wherein the second clock signal generation means at the fourth point receives the global clock signal with a fourth propagation delay of the transmission line means from the first end to the fourth point, wherein the second clock signal generation means generates the second clock signal at a second timing that is halfway between the global clock signal with the third propagation delay and the global clock signal with the fourth propagation delay, wherein the second timing of the second clock signal coincides with the global clock signal with the midpoint propagation delay of the transmission line means from the first end to the midpoint, wherein the first timing is the same as the second timing such that the first clock signal is synchronized with the second clock signal.