Memory system and memory chip

A memory chip comprising:

• a first align circuit comprising a plurality of transceivers;
• a first set of memory banks;
• data lines;
• a plurality set of data line sensing amplifiers coupled to the data lines, wherein each set of data line sensing amplifiers is corresponding to one memory bank of the first set of memory banks and each set of data line sensing amplifiers are electrically connected to the plurality of transceivers through the data lines;
• and
• an I/O data bus of the memory chip electrically coupled to the first set of memory banks, wherein during a read operation of the memory chip, each memory bank transmits a first predetermined width of data to the plurality of transceivers which simultaneously transmit the first predetermined width of data of each memory bank in parallel to the I/O data bus, and during a write operation of the memory chip, the I/O data bus are configured to output a second predetermined width of data to the plurality of transceivers which then simultaneously transmit a corresponding portion of the second predetermined width of data in parallel to each memory bank of the first set of memory banks, wherein a predetermined data width of the I/O data bus is equal to a sum of the first predetermined width of data outputted by each memory bank of the first set of the memory banks during the read operation of the memory chip, and the predetermined data width of the I/O data bus is equal to a sum of the corresponding portion of the second predetermined width of data received by each memory bank of the first set of the memory banks during the write operation of the memory chip;
• wherein there is no parallel-to-serial circuit and serial-to-parallel circuit in the memory chip.