Back to results
US 12,725,640 B2Granted
Memory circuit architecture with multiplexing between memory banks
AssigneeQUALCOMM Incorporated
InventorsPradeep Raj, Rahul Sahu, Sharad Kumar Gupta, Hemant Patel, Diwakar Singh
Life of this patent
Estimating the term…
Abstract
One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.
Claims11
A system on chip (SOC) comprising:
- a random-access memory (RAM) having a first inner memory bank, a first outer memory bank, a second inner memory bank, and a second outer memory bank, wherein the first inner memory bank is positioned between the first outer memory bank and a controller of the RAM, and wherein the second inner memory bank is positioned between the second outer memory bank and the controller of the RAM;
- a distributed multiplexer system within the RAM, including a first outer multiplexer disposed on a first side of the first inner memory bank opposite the controller, a first inner multiplexer disposed between the first inner memory bank and a write driver and a sense amplifier of the controller of the RAM, a second inner multiplexer disposed between the second inner memory bank and the write driver and sense amplifier, and a second outer multiplexer disposed on a second side of the second inner memory bank opposite the controller;
- a first plurality of data lines coupling the controller to the first outer multiplexer;
- and
- a second plurality of data lines coupling the controller to the first inner multiplexer.
2 more elements
Dependencies are inferred from the claim text.