G11C 2029/2602
Concurrent test
Official title: {Concurrent test}
G11C2029/2602 (Concurrent test) appears on 483 US grants and 486 published applications in this corpus.
Search patents in G11C- Granted patents
- 483
- Published applications
- 486
- Assignees
- 135
- Inventors
- 909
- Latest grant
- 17 Feb 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 1 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 4 | 0 |
| 2000 | 4 | 0 |
| 2001 | 5 | 1 |
| 2002 | 12 | 9 |
| 2003 | 24 | 26 |
| 2004 | 20 | 34 |
| 2005 | 18 | 40 |
| 2006 | 32 | 24 |
| 2007 | 33 | 30 |
| 2008 | 31 | 39 |
| 2009 | 25 | 30 |
| 2010 | 26 | 12 |
| 2011 | 22 | 13 |
| 2012 | 14 | 24 |
| 2013 | 19 | 15 |
| 2014 | 25 | 19 |
| 2015 | 16 | 20 |
| 2016 | 20 | 15 |
| 2017 | 14 | 10 |
| 2018 | 12 | 11 |
| 2019 | 16 | 15 |
| 2020 | 12 | 17 |
| 2021 | 16 | 24 |
| 2022 | 12 | 20 |
| 2023 | 22 | 16 |
| 2024 | 11 | 8 |
| 2025 | 10 | 11 |
| 2026 | 3 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Systems and methods to perform automatic test pattern generation on multiple memory units in parallel17 Feb 2026US 12,555,645 B2Texas Instruments Incorporated
- Systems and methods for reducing error log required space at low temperatures20 Jan 2026US 12,531,133 B2Intelligent Memory Limited
- Physical-aware power profile optimization during memory test13 Jan 2026US 12,524,323 B2NXP USA, Inc.
- Trim values for multi-plane operations18 Nov 2025US 12,474,861 B2Micron Technology, Inc.
- Apparatuses and methods for parallel writing to multiple memory device structures19 Aug 2025US 12,393,342 B2
- Read-write testing method, device, and storage medium for memory storage device23 Jul 2026US 2026/0212941 A1Shenzhen Rayson Technology Co., Ltd.
- Storage system having adaptive channel configuration and operating method of storage controller25 Jun 2026US 2026/0178215 A1Samsung Electronics Co., Ltd.
- Repair Sharing In Serial Repair Interfaces25 Jun 2026US 2026/0179710 A1Google Inc.
- Apparatuses and methods for parallel writing to multiple memory device locations27 Nov 2025US 2025/0362807 A1Lodestar Licensing Group LLC
- Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same20 Nov 2025US 2025/0355826 A1Lodestar Licensing Group LLC
Most cited
By later US patents
- Semiconductor memory device having multi-bit testing function424US 6,816,422 B2Renesas Technology Corp. · 2004
- Memory module, test system and method for testing one or a plurality of memory modules145US 7,231,562 B2Infineon Technologies AG · 2007
- Method and apparatus for optimized parallel testing and access of electronic circuits113US 6,988,232 B2Intellitech Corporation · 2006
- Distributed interface for parallel testing of multiple devices using a single tester channel107US 6,499,121 B1FormFactor, Inc. · 2002
- Method for writing to multiple banks of a memory device97US 5,959,929 AMicron Technology, Inc. · 1999