Semiconductor memory device having multi-bit testing function
AssigneeRenesas Technology Corp.
InventorsKei Hamade, Takashi Kono, Kiyohiro Furutani
Life of this patent
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Abstract
In a multi-bit test, an I/O combiner degenerates data of a plurality of bits read from a memory cell array to first to fourth data bus pairs in parallel and outputs the degenerated data to a fifth data bus. A read amplifier compares a logic level of the degenerated data received from the I/O combiner with a logic level of expected value data. If the logic level of the degenerated data coincides with the logic level of the expected value data, the read amplifier determines that data write and read to and from the plurality of bits have been normally performed. As a result, a semiconductor memory device can detect a word line defect in the multi-bit test.
Claims7
A semiconductor memory device comprising:
- a memory cell array for storing data;
- a determination circuit for receiving expected value data for logic levels of read data of a plurality of bits read in parallel from said memory cell array, and determining whether the logic levels of said read data coincide with a logic level of said expected value data in a multi-bit test;
- an output circuit for outputting a determination result of said determination circuit;
- an input circuit for receiving degenerated data obtained by degenerating write data of a plurality of bits written in parallel to said memory cell array;
- a test mode control circuit for generating a write data pattern signal for said write data of the plurality of bits on the basis of an internal test pattern setting signal generated internally;
- a write data inversion circuit for inverting logic level of a part of said write data of the plurality of bits written in parallel to said memory cell array on the basis of said write data pattern signal in said multi-bit test;
- and
- a read data inversion circuit for re-inverting the logic level of the data the logic level of which is inverted by said write data inversion circuit for said read data of the plurality of bits read in parallel from said memory cell array, and outputting the re-inverted read data of the plurality of bits to said determination circuit.
Dependencies are inferred from the claim text.