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US 12,555,645 B2Granted
Systems and methods to perform automatic test pattern generation on multiple memory units in parallel
AssigneeTexas Instruments Incorporated
InventorsNitesh Mishra, Hrithik Sahni
Life of this patent
Estimating the term…
Abstract
Systems and methods may perform sequential automatic test pattern generation (ATPG) on parallel memory units. A first array of logic gates may output enable signals to cause multiple memory units to be enabled in parallel. Test pattern generation and test control logic may perform forward path testing, backward path testing, and any other appropriate testing on the enabled memory units. The systems and methods may then move on to another group of memory units, which are enabled in parallel and tested in parallel.
Claims20
A method comprising:
- entering a test mode for a memory device having a plurality of parallel memory units, the plurality of parallel memory units including a first subset of memory units and a second subset of memory units;
- enabling a first memory unit of the first subset of memory units and a second memory unit of the second subset of memory units, wherein enabling the first memory unit and enabling the second memory unit overlaps in time;
- performing a first test operation on the first memory unit and on the second memory unit, including writing test data to the first memory unit and to the second memory unit;
- and
- disabling a remainder of the first subset of memory units and disabling a remainder of the second subset of memory units during the first test operation.
2 more elements
A circuit comprising:
- a memory device having a plurality of parallel memory units, the plurality of parallel memory units including a first subset of memory units and a second subset of memory units;
- a first logic block configured to:
- in an operating mode, enable a first memory unit of the first subset of memory units and, concurrently, disable a remainder of the first subset of memory units and an entirety of the second subset of memory units;
- and
- in a test mode, enable the first memory unit of the first subset of memory units and, in parallel, enable a second memory unit of the second subset of memory units and, concurrently, disable the remainder of the first subset of memory units and a remainder of the second subset of memory units;
- and
- a second logic block configured to perform a first sequential automatic test pattern generation (ATPG) operation on the first memory unit and on the second memory unit in parallel, including writing test data to the first memory unit and to the second memory unit and reading the test data from the first memory unit and from the second memory unit.
4 more elements
A circuit comprising:
- a memory device having a plurality of parallel memory units, the plurality of parallel memory units including a first subset of memory units and a second subset of memory units;
- a first logic gate array having inputs coupled to first test enable logic and outputs coupled to enable inputs of the first subset of memory units;
- a second logic gate array having inputs coupled to second test enable logic and outputs coupled to enable inputs of the second subset of memory units;
- a third logic gate array having inputs coupled to third test enable logic and outputs of the first subset of memory units, wherein the third logic gate array has outputs coupled to a first set of flip-flops;
- a fourth logic gate array having inputs coupled to fourth test enable logic and outputs of the second subset of memory units, wherein the fourth logic gate array has outputs coupled to a second set of flip-flops;
- and
- a test generation logic block coupled to data inputs of the first subset of memory units and coupled to data inputs of the second subset of memory units.
4 more elements
Dependencies are inferred from the claim text.