Physical-aware power profile optimization during memory test

An apparatus comprising:

• a plurality of Built-In Self-Test (BIST) controllers;
• a respective group of memories coupled to each BIST controller;
• a first circuit configured to determine a test time budget from one of a plurality of test sequences comprising a longest execution time;
• a second circuit configured to create a plurality of scheduling buckets, wherein each scheduling bucket comprises one or more sequentially executed test sequences, each test sequence controlled by a respective Built-In Self-Test (BIST) controller, each test sequence comprising a respective unoptimized start time and a respective execution time, and a respective combined duration of the execution times of each respective scheduling bucket being less than or equal to the test time budget;
• and
• a third circuit configured to optimize a power profile by determining a respective optimized start time of at least one test sequence from at least one physical attribute, the at least one physical attribute including a physical distance between two groups of memories controlled by respective BIST controllers.

A method for physical-aware power profile optimization during memory test comprising:

• determining a test time budget from one of a plurality of test sequences comprising a longest execution time;
• creating a plurality of scheduling buckets, wherein each scheduling bucket comprises a serially arranged one or more of the test sequences, each test sequence controlled by a respective Built-In Self-Test (BIST) controller, each test sequence comprising a respective unoptimized start time and a respective execution time, and a respective combined duration of the execution times of each respective scheduling bucket being less than or equal to the test time budget;
• and
• optimizing a power profile by determining a respective optimized start time of at least one test sequence from at least one physical attribute, the at least one physical attribute including a physical distance between two groups of memories controlled by respective BIST controllers.