Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same

A method, comprising:

• receiving a clock signal at a first clock terminal of a first memory device;
• receiving the clock signal at a second clock terminal of a second memory device;
• adjusting a first controllable impedance at the first clock terminal;
• and
• adjusting a second controllable impedance at the second clock terminal, wherein adjusting the first controllable impedance and the second controllable impedance provides a combined controllable impedance that is in accordance with an impedance of the clock signal.

A memory system, comprising:

• a first memory device comprising:
• a first clock terminal configured to receive a clock signal;
• and
• first circuitry coupled with the first clock terminal;
• and
• a second memory device comprising:
• a second clock terminal configured to receive the clock signal;
• and
• second circuitry coupled with the second clock terminal,
• wherein the first circuitry and the second circuitry are coupled in parallel, and
• wherein the first circuitry and the second circuitry are configured to provide a combined controllable impedance that is greater than or equal to an impedance of the clock signal.