Method and apparatus for optimized parallel testing and access of electronic circuits

A system for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the first test resource is configured to send at least one first signal over the test bus to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers,
• wherein each controller is configured to employ a first protocol to access the respective electronic circuit coupleable thereto based on the at least one first signal sent over the test bus by the first test resource, and
• wherein the test bus comprises a digital test bus, and the system further includes an analog test bus, a second test resource, and a communication link configured to couple the second test resource to the first test resource, the analog test bus being coupled to the second test resource and coupleable to the respective electronic circuits to be accessed.

A system for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the first test resource is configured to send at least one first signal over the test bus to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers,
• wherein each controller is configured to employ a first protocol to access the respective electronic circuit coupleable thereto based on the at least one first signal sent over the test bus by the first test resource, and
• wherein each controller is further configured to receive at least one actual-data signal from the respective electronic circuit as a result of being accessed, and the first test resource is further configured to send at least one mask-data signal to the respective controllers, the mask-data signal being operative to mask at least a portion of the actual-data signal.

A system for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising;

• a test bus;
• a first test resource connect6d to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the first test resource is configured to send at least one first signal over the test bus to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers,
• wherein each controller is configured to employ a first protocol to access the respective electronic circuit coupleable thereto based on the at least one first signal sent over the test bus by the first test resource, and
• wherein each controller is further configured to provide at least one input-data signal to the respective electronic circuit coupleable thereto, and the first test resource is further configured to send at least one mask-data signal to the controller, the mask-data signal being operative to mask at least a portion of the input-data signal.

A system for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the first test resource is configured to send at least one first signal over the test bus to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers,
• wherein each controller is configured to employ a first protocol to access the respective electronic circuit coupleable thereto based on the at least one first signal sent over the test bus by the first test resource, and
• wherein each controller includes a digital input/output circuit configured to convey one or more digital signals between the controller and the respective electronic circuit based on at least one second signal sent over the test bus by the first test resource.

A system for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the first test resource is configured to send at least one first signal over the test bus to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers,
• wherein each controller is configured to employ a first protocol to access the respective electronic circuit coupleable thereto based on the at least one first signal sent over the test bus by the first test resource, and
• wherein each controller includes an auto start circuit configured to send a start signal over the test bus from the controller to the first test resource, the start signal being operative to indicate to the first test resource that the respective electronic circuits to be accessed are coupled to the controllers, thereby enabling the first test resource to provide the at least one first signal to access, substantially in parallel, the electronic circuits via the respective controllers.

A system for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the first test resource is configured to send at least one first signal over the test bus to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers,
• wherein each controller is configured to employ a first protocol to access the respective electronic circuit coupleable thereto based on the at least one first signal sent over the test bus by the first test resource, and
• wherein each controller includes a communication interface having an associated voltage level coupleable to the respective electronic circuit to be accessed, and a programmable input/output voltage circuit configured to set the voltage level of the communication interface to assure electrical compatibility with the respective electronic circuit.

A system for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the first test resource is configured to send at least one first signal over the test bus to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers,
• wherein, each controller, is configured to employ a first protocol to access the respective electronic circuit coupleable thereto based on the at least one first signal sent over the test bus by the first test resource, and
• wherein the test bus comprises a plurality of test buses, and respective pluralities of controllers are connected to the test buses, and further including at least one bus bridge configured for successively interconnecting the test buses.

A system for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the first test resource is configured to send at least one first signal over the test bus to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers,
• wherein each controller is configured to employ a first protocol to access the respective electronic circuit coupleable thereto based on the at least one first signal sent over the test bus by the first test resource, and
• wherein the first test resource is configured to store data denoting a plurality of modes for addressing the plurality of controllers, and to execute at least one application to address at least one of the plurality of controllers according to one of the addressing modes.

A test bus architecture for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the test bus is configured to convey at least one first signal from the first test resource to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers, and
• wherein the test bus is further configured to convey at least one expected-data signal from the first test resource to the respective controllers, the expected-data signal being indicative of data expected to be received from the electronic circuits as a result of being accessed by the respective controllers.

A test bus architecture for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the test bus is configured to convey at least one first signal from the first test resource to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers, and
• wherein the respective controllers are further configured to receive at least one actual-data signal from the respective electronic circuits, and the test bus is further configured to convey at least one mask-data signal from the first test resource to the respective controllers, the mask-data signal being operative to mask at least a portion of the actual-data signal.

A test bus architecture for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the test bus is configured to convey at least one first signal from the first test resource to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers, and
• wherein each controller is configured to provide at least one input-data signal to the respective electronic circuit coupleable thereto, and the test bus is further configured to convey at least one mask-data signal from the first test resource to the controller, the mask-data signal being operative to mask at least a portion of the input-data signal.

A test bus architecture for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising:

• a test bus;
• a first test resource connected to the test bus;
• and
• a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed,
• wherein the test bus is configured to convey at least one first signal from the first test resource to respective controllers to access, substantially in parallel, the electronic circuits via the respective controllers, and
• wherein the test bus is further configured to convey a start signal from the respective controllers to the first test resource, the start signal being operative to indicate to the first test resource that the respective electronic circuits to be accessed are coupled to the controllers, thereby enabling the first test resource to provide the at least one first signal to access, substantially in parallel, the respective ports of the electronic circuits via the respective controllers.

A test resource for controlling access to one or more electronic circuits for testing, debugging, or programmably configuring the circuits, comprising:

• a communication interface connectable to a test bus, the test bus being connected to a plurality of controllers, each controller being coupleable to a respective electronic circuit to be accessed;
• and
• at least one storage device configured to store at least one application for accessing, substantially in parallel, the respective electronic circuits via the plurality of controllers,
• wherein the test resource is configured to execute the at least one application to control the transmission of at least one first signal over the test bus via the communication interface to respective controllers, the respective controllers employing a first protocol to access the electronic circuits coupleable thereto based on the at least one first signal sent over the test bus by the test resource,
• wherein the at least one storage device is configured to store data denoting a plurality of modes for addressing the plurality of controllers, the test resource being configured to execute the at least one application to address at least one of the plurality of controllers according to one of the addressing modes, and
• wherein each controller has an associated address value, and in one of the addressing modes the test resource addresses a single controller based on its associated address value.

A test resource for controlling access to one or more electronic circuits for testing, debugging, or programmably configuring the circuits, comprising:

• a communication interface connectable to a test bus, the test bus being connected to a plurality of controllers, each controller being coupleable to a respective electronic circuit to be accessed;
• and
• at least one storage device configured to store at least one application for accessing, substantially in parallel, the respective electronic circuits via the plurality of controllers,
• wherein the test resource is configured to execute the at least one application to control the transmission of at least one first signal over the test bus via the communication interface to respective controllers, the respective controllers employing a first protocol to access the electronic circuits coupleable thereto based on the at least one first signal sent over the test bus by the test resource,
• wherein the at least one storage device is configured to store data denoting a plurality of modes for addressing the plurality of controllers, the test resource being configured to execute the at least one application to address at least one of the plurality of controllers according to one of the addressing modes, and
• wherein each controller has an associated identification value, and in one of the addressing modes the test resource addresses one or more of the plurality of controllers based on their associated identification values.

A test resource for controlling access to one or more electronic circuits for testing, debugging, or programmably configuring the circuits, comprising:

• a communication interface connectable to a test bus, the test bus being connected to plurality of controllers, each controller being coupleable to a respective electronic circuit to be accessed;
• and
• at least one storage device configured to store at least one application for accessing, substantially in parallel, the respective electronic circuits via the plurality of controllers,
• wherein the test resource is configured to execute the at least one application to control the transmission of at least one first signal over the test bus via the communication interface to respective controllers, the respective controllers employing a first protocol to access the electronic circuits coupleable thereto based on the at least one first signal sent over the test bus by the test resource,
• wherein the at least one storage device is configured to store data denoting a plurality of modes for addressing the plurality of controllers, the test resource being configured to execute the at least one application to address at least one of the plurality of controllers according to one of the addressing modes, and
• wherein each controller has an associated group address value, and in one of the addressing modes the test resource addresses respective controllers having the same group address value.

A test resource for controlling access to one or more electronic circuits for testing, debugging, or programmably configuring the circuits, comprising:

• a communication interface connectable to a test bus, the test bus being connected to a plurality of controllers, each controller being coupleable to a respective electronic circuit to be accessed;
• and
• at least one storage device configured to store at least one application for accessing, substantially in parallel, the respective electronic circuits via the plurality of controllers,
• wherein the test resource is configured to execute the at least one application to control the transmission of at least one first signal over the test bus via the communication interface to respective controllers, the respective controllers employing a first protocol to access the electronic circuits coupleable thereto based on the at least one first signal sent over the test bus by the test resource,
• wherein the at least one storage device is configured to store data denoting a plurality of modes for addressing the plurality of controllers, the test resource being configured to execute the at least one application to address at least one of the plurality of controllers according to one of the addressing modes, and
• wherein at least one of the plurality of controllers has an associated alias address value, and in one of the addressing modes the test resource addresses at least one controller based on its associated alias address value.

A method of accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising the steps of:

• providing a first test bus;
• providing a first test resource and a plurality of first controllers connected to the first test bus, each first controller being coupleable to a respective electronic circuit to be accessed;
• sending at least one first signal over the first test bus to respective first controllers, by the first test resource to access, substantially in parallel, the electronic circuits via the respective first controllers;
• employing a first protocol to access the electronic circuits by the respective first controllers based on the at least one first signal sent over the first test bus by the first test resource, and
• further including the steps of providing a second test bus coupleable to the respective electronic circuits to be accessed and respective second controllers connected to the second test bus and the first controllers, and employing a second protocol to access the respective electronic circuits via the respective second controllers by the first controllers based on at least one second signal sent over the first test bus by the first test resource.

A method of accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising the steps of:

• providing a first test bus;
• providing a first test resource and a plurality of first controllers connected to the first test bus, each first controller being coupleable to a respective electronic circuit to be accessed;
• sending at least one first signal over the first test bus to respective first controllers by the first test resource to access, substantially in parallel, the electronic circuits via the respective first controllers;
• employing a first protocol to access the electronic circuits by the respective first controllers based on the at least one first signal sent over the first test bus by the first test resource, and
• further including the step of sending at least one expected data signal to the respective first controllers by the first test resource, the expected-data signal being indicative of data expected to be received from the electronic circuits as a result of being accessed by the respective first controllers.

A method of accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising the steps of:

• providing a first test bus;
• providing a first test resource and a plurality of first controllers connected to the first test bus, each first controller being coupleable to a respective electronic circuit to be accessed;
• sending at least one first signal over the first test bus to respective first controllers by the first test resource to access, substantially in parallel, the electronic circuits via the respective first controllers;
• employing a first protocol to access the electronic circuits by the respective first controllers based on the at least one first signal sent over the first test bus by the first test resource, and
• further including the steps of receiving at least one actual data signal from the respective electronic circuit as a result of being accessed by the first controller, sending at least one mask-data signal to the respective first controllers by the first test resource, the mask-data signal being operative to mask at least a portion of the actual-data signal.

A method of accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising the steps of:

• providing a first test bus;
• providing a first test resource and a plurality of first controllers connected to the first test bus, each first controller being coupleable to a respective electronic circuit to be accessed;
• sending at least one first signal over the first test bus to respective first controllers by the first test resource to access, substantially in parallel, the electronic circuits via the respective first controllers;
• employing a first protocol to access the electronic circuits by the respective first controllers based on the at least one first signal sent over the first test bus by the first test resource, and
• further including the steps of providing at least one input-data signal to the respective electronic circuit by the first controller, and sending at least one mask-data signal to the first controller by the first test resource, the mask-data signal being operative to mask at least a portion of the input-data signal.

A method of accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising the steps of:

• providing a first test bus;
• providing a first test resource and a plurality of first controllers connected to the first test bus, each first controller being coupleable to a respective electronic circuit to be accessed;
• sending at least one first signal over the first test bus to respective first controllers by the first test resource to access, substantially in parallel, the electronic circuits via the respective first controllers;
• employing a first protocol to access the electronic circuits by the respective first controllers based on the at least one first signal sent over the first test bus by the first test resource, and
• wherein the first providing step includes providing a plurality of test buses, and the second providing step includes providing respective pluralities of first controllers connected to the test buses, and further including the step of successively interconnecting the test buses by at least one bus bridge.

A test bus architecture, comprising:

• a plurality of test buses;
• and
• at least one test bus bridge interconnecting the plurality of test buses, each test bus bridge interconnecting a respective pair of test buses,
• wherein each test bus bridge is configured to convey test data between a first test bus and a second test bus,
• wherein each test bus bridge includes a plurality of registers including at least one first register and at least one second register, the first register being communicably coupled to the first test bus, the second register being communicably coupled to the second test bus, the first and second registers being communicably coupled to one another to allow test data to be conveyed between the first and second test buses via the first and second registers, and
• wherein the first register is clocked by a first clock signal and the second register is clocked by a second clock signal.