G11C 13/0028
Word-line or row circuits
Official title: {Word-line or row circuits}
G11C13/0028 (Word-line or row circuits) appears on 1,433 US grants and 1,573 published applications in this corpus.
Search patents in G11C- Granted patents
- 1,433
- Published applications
- 1,573
- Assignees
- 200
- Inventors
- 1,698
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2001 | 1 | 0 |
| 2002 | 1 | 2 |
| 2003 | 3 | 5 |
| 2004 | 4 | 2 |
| 2005 | 1 | 7 |
| 2006 | 4 | 7 |
| 2007 | 6 | 15 |
| 2008 | 12 | 28 |
| 2009 | 13 | 33 |
| 2010 | 24 | 43 |
| 2011 | 46 | 34 |
| 2012 | 30 | 50 |
| 2013 | 40 | 30 |
| 2014 | 49 | 44 |
| 2015 | 54 | 48 |
| 2016 | 74 | 85 |
| 2017 | 94 | 87 |
| 2018 | 87 | 84 |
| 2019 | 89 | 149 |
| 2020 | 169 | 159 |
| 2021 | 167 | 173 |
| 2022 | 120 | 139 |
| 2023 | 113 | 122 |
| 2024 | 105 | 90 |
| 2025 | 88 | 77 |
| 2026 | 39 | 60 |
By publication year. 2026 runs to 8 Oct.
Recent patents
- Wordline-coupled differential programming of two-terminal memory with increased cell density and consistent cell pitch29 Sep 2026US 12,749,531 B1Crossbar, Inc.
- Non-volatile memory having first and second leday circuits, and electronic system and method29 Sep 2026US 12,749,532 B2STMicroelectronics International N. V.
- Memory circuit comprising electronic cells with ovonic threshold switching layers and a control circuit29 Sep 2026US 12,751,017 B2STMicroelectronics International N. V.
- Differential subthreshold read of memory cell pair in a memory device22 Sep 2026US 12,744,083 B2Micron Technology, Inc.
- Memory device with sub-arrays and selection switches for reducing bit line interference25 Aug 2026US 12,718,852 B2Rohm Co., Ltd.
- Segmented reference for tracking column loading8 Oct 2026US 2026/0311759 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Memory including variable resistor24 Sep 2026US 2026/0290451 A1SK hynix Inc.
- In-memory computing architecture and operating method thereof24 Sep 2026US 2026/0290452 A1Peking University
- In-memory computation system using a segmented memory architecture with local memory array selection for simultaneously performing multiple independent operations27 Aug 2026US 2026/0253636 A1STMicroelectronics International N. V.
- Semiconductor storage device13 Aug 2026US 2026/0237433 A1Kioxia Corporation
Most cited
By later US patents
- Programmable resistance memory arrays with reference cells317US 6,314,014 B1Ovonyx, Inc. · 2001
- Phase change memory cell and manufacturing method286US 7,688,619 B2Macronix International Co., Ltd. · 2010
- Biasing scheme of floating unselected wordlines and bitlines of a diode-based memory array188US 6,462,984 B1Intel Corporation · 2002
- Vertical thin film transistors with surround gates188US 9,673,257 B1SanDisk Technologies LLC · 2017
- Memories with cylindrical read/write stacks185US 9,227,456 B2SanDisk 3D LLC · 2016