In-memory computing architecture and operating method thereof

An operating method of an in-memory computing architecture, the in-memory computing architecture comprising a memory array, a driving and sensing circuit, and a peripheral circuit;

• the memory array comprising a plurality of memory strings, a plurality of source lines, a plurality of word lines, and a plurality of bit lines;
• each of the plurality of memory strings comprising a plurality of memory cells connected in series along a first direction;
• each of the plurality of memory cell comprising a memory transistor and a bypass resistor;
• the memory transistor and the bypass resistor being connected in parallel;
• each of the plurality of memory strings being connected to the corresponding source line of the plurality of source lines through a bottom select transistor;
• each of the plurality of memory strings being connected to the corresponding bit line of the plurality of bit lines through a top select transistor;
• a control terminal of each of the plurality of memory cell being connected to the corresponding word line;
• the driving and sensing circuit connected to the source line;
• the driving and sensing circuit being configured to provide a read current to the source line, sense a voltage signal of the source line, and output a digital signal of the voltage signal of the source line;
• the peripheral circuit connected to the word lines and the bit lines;
• and the peripheral circuit being configured to control voltages of the word lines and the bit lines;
• wherein the operating method of the in-memory computing architecture comprises:
• deploying weight information to the plurality of memory cells according to a weight writing strategy, with threshold voltages of the plurality of memory cells representing the weight information;
• applying read voltages or turn-on voltages to the plurality of word lines, and inputting a read current to the source line corresponding to the plurality of word lines;
• and
• calculating the number of turned-off memory transistors in the corresponding memory string according to a voltage drop generated by the source line, and outputting a computation result.

A memory array, comprising:

• a plurality of memory strings;
• a plurality of source lines;
• a plurality of word lines;
• and
• a plurality of bit lines,
• wherein each of the plurality of memory strings comprises a plurality of memory cells connected in series along a first direction, each of the plurality of memory cells comprises a memory transistor and a bypass resistor, the memory transistor and the bypass resistor are connected in parallel, each of the plurality of memory strings is connected to the corresponding source line of the plurality of source lines through a bottom select transistor, each of the plurality of memory strings is connected to the corresponding bit line of the plurality of bit lines through a top select transistor, and a control terminal of each of the plurality of memory cell is connected to the corresponding word line.