Memory device with sub-arrays and selection switches for reducing bit line interference

A memory device, comprising:

• an upper memory array configured to have memory cells disposed in a matrix along mutually orthogonal X and Y directions;
• a lower memory array configured to have memory cells disposed in a matrix along the X and Y directions, the lower memory array being disposed at another side of the upper memory array along the Y direction;
• a Y decoder configured to be disposed to be located between the upper and lower memory arrays along the Y direction as seen in a plan view;
• a sense amplifier;
• and
• a switch circuit,
• wherein
• upper bit lines connected to the memory cells in the upper memory array extend in the Y direction in the upper memory array and the Y decoder;
• lower bit lines connected to the memory cells in the lower memory array extend in the Y direction in the lower memory array and the Y decoder;
• the Y decoder includes:
• an upper Y line selection switch connected to the upper bit lines;
• and
• a lower Y line selection switch connected to the lower bit lines, the lower Y line selection switch being disposed at another side of the Y decoder from the upper Y line selection switch along the Y direction,
• the switch circuit is configured to be capable of switching so as to permit either conduction between the sense amplifier and the upper Y line selection switch or conduction between the sense amplifier and the lower Y line selection switch,
• the memory device further includes a first high voltage pulse generator and a second high voltage pulse generator configured to generate high-voltage pulses in a write operation, and
• the Y decoder includes:
• a data latch circuit;
• a first transistor having a control terminal configured to be driven by data latched by the data latch circuit, a first terminal connected to an output terminal of the first high voltage pulse generator, and a second terminal connected to the upper bit lines;
• and
• a second transistor having a control terminal configured to be driven by the data latched by the data latch circuit, a first terminal connected to an output terminal of the second high voltage pulse generator, and a second terminal connected to the lower bit lines.

A memory device, comprising:

• an upper memory array configured to have memory cells disposed in a matrix along mutually orthogonal X and Y directions;
• a lower memory array configured to have memory cells disposed in a matrix along the X and Y directions, the lower memory array being disposed at another side of the upper memory array along the Y direction;
• a Y decoder configured to be disposed to be located between the upper and lower memory arrays along the Y direction as seen in a plan view;
• a sense amplifier;
• and
• a switch circuit,
• wherein
• upper bit lines connected to the memory cells in the upper memory array extend in the Y direction in the upper memory array and the Y decoder;
• lower bit lines connected to the memory cells in the lower memory array extend in the Y direction in the lower memory array and the Y decoder;
• the Y decoder includes:
• an upper Y line selection switch connected to the upper bit lines;
• and
• a lower Y line selection switch connected to the lower bit lines, the lower Y line selection switch being disposed at another side of the Y decoder from the upper Y line selection switch along the Y direction,
• the switch circuit is configured to be capable of switching so as to permit either conduction between the sense amplifier and the upper Y line selection switch or conduction between the sense amplifier and the lower Y line selection switch, and
• a wiring length from the sense amplifier via the switch circuit to the upper Y line selection switch is equal to a wiring length from the sense amplifier via the switch circuit SWC to the lower Y line selection switch.