In-memory computation system using a segmented memory architecture with local memory array selection for simultaneously performing multiple independent operations

An in-memory computation circuit, comprising:

• a memory including a plurality of memory cells arranged in a matrix with a plurality of cell rows and a plurality of cell columns, wherein each cell row is associated with a word line connected to the memory cells in the cell row, and wherein each cell column is associated with a global bit line;
• wherein the memory is segmented into a plurality of local memory arrays arranged in a matrix with a plurality of array rows and a plurality of array columns;
• a word line driver for each array row that is selectively enabled in response to a row select signal to drive word lines of the array row;
• wherein each local memory array includes a plurality of local bit lines connected to memory cells in the cell columns and a column decoder circuit configured to selectively connect the local bit lines to the global bit lines of the array column in response to a column select signal;
• a control circuit configured to generate row select signals for the word lines drivers and column select signals for the column decoder circuits to map a first group of one or more local memory arrays to participate in a first in-memory compute operation producing computation output signals on first ones of the global bit lines and map a second group of one or more local memory arrays, different from the first ones of the local memory arrays, to participate in a second in-memory compute operation producing computation output signals on second ones of the global bit lines, different from the first ones of the global bit lines;
• and
• an analog-to-digital conversion (ADC) circuit coupled to each global bit line;
• each ADC circuit comprising:
• an integration circuit configured to generate a clock signal in response to the computation output signal on the global bit line;
• and
• a counter circuit configured to count pulses of the clock signal;
• and
• a dynamic ADC multiplication control circuit configured to control a multiplication factor for counting clock signal pulses by the ADC circuits coupled to the first ones of the global bit lines dependent on a matrix dimension of the first in-memory compute operation and control a multiplication factor for counting clock signal pulses by the ADC circuits coupled to the second ones of the global bit lines dependent on a matrix dimension of the second in-memory compute operation;
• wherein the first and second in-memory compute operations are substantially simultaneously executed.