US 12,749,531 B1Granted

Wordline-coupled differential programming of two-terminal memory with increased cell density and consistent cell pitch

AssigneeCrossbar, Inc.

InventorHagop Nazarian

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Abstract

An architecture is provided for differential programming of multiple one-resistor, one-transistor (1T1R) two-terminal resistive switching memory cells that define a single bit (e.g., a differential bit). The single bit can be a physical unclonable function (PUF) bit or a random number generation (RNG) bit, or the like. A program voltage can be applied concurrently to the multiple 1T1R cells on a common bitline, and a pass transistor activated to electrically short second terminals of the two-terminal resistive switching memory cells. As a result, programming of one of the multiple memory cells can intrinsically and very rapidly suppress programming of remaining memory cells of the differential bit, and greatly mitigate or avoid an invalid data result. In addition, two-terminal resistive switching memory cells of the architecture can have uniform or substantially uniform pitch there between, increasing cell density and minimizing or avoiding process and electrical variation among such memory cells.

Claims19

Dependent claims

An integrated circuit device, comprising:

an array of transistors;
an array of two-terminal resistive switching memory (ReMEM) cells;
a bitline;
wherein:
a first group of transistors of the array of transistors and a first group of ReMEM cells of the array of ReMEM cells form a first plurality of one transistor one resistive memory (1T1R) ReMEM circuits coupled respectively at one end to the bitline and at a second end to ground;
a second group of transistors of the array of transistors and a second group of ReMEM cells of the array of ReMEM cells form a second plurality of 1T1R ReMEM circuits coupled respectively at one end to the bitline and at a second end to ground;
a first wordline coupled to a gate of a first transistor of a first 1T1R ReMEM circuit of the first plurality of 1T1R ReMEM circuits, the first 1T1R ReMEM circuit comprising the first transistor and a first two-terminal ReMEM of the first group of ReMEM cells;
a second wordline coupled to a second gate of a second transistor of a second 1T1R ReMEM circuit of the first plurality of 1T1R ReMEM circuits, the second 1T1R ReMEM circuit comprising the second transistor and a second two-terminal ReMEM of the first group of ReMEM cells;
a pass transistor of the first group of transistors that is:
coupled at a source node of the pass transistor to a first common node electrically coupling a second terminal of the first two-terminal ReMEM with a channel node of the first transistor;
coupled at a drain node of the pass transistor to a second common node electrically coupling a second terminal of the second two-terminal ReMEM with a second channel node of the second transistor;
and
a pass wordline coupled to a gate node of the pass transistor, wherein activation of the pass wordline electrically shorts the first common node and the second common node through the pass transistor.

10 more elements

A semiconductor chip, comprising:

an array of transistors formed in a diffusion layer of the semiconductor chip;
an array of two-terminal memory cells overlying the diffusion layer and overlying at least a portion of the array of transistors;
a bitline;
a first group of wordlines;
a first 1T1R ReMEM circuit comprising a first transistor of the array of transistors and a first two-terminal memory cell of the array of two-terminal memory cells;
a second 1T1R ReMEM circuit comprising a second transistor of the array of transistors and a second two-terminal memory cell of the array of two-terminal memory cells, wherein the first and second 1T1R ReMEM circuits are coupled to respective wordlines of the first group of wordlines and form a differential programmed physical unclonable feature (PUF) non-volatile memory circuit coupled to the bitline;
a second group of wordlines;
a third 1T1R ReMEM circuit comprising a third transistor coupled to a third wordline of the second group of wordlines;
and
a fourth 1T1R ReMEM circuit comprising a fourth transistor coupled to a fourth wordline of the second group of wordlines, wherein:
the third 1T1R ReMEM circuit or the fourth 1T1R ReMEM circuit forms a many-time programmable non-volatile memory circuit or a one-time programmable non-volatile memory circuit coupled to the bitline;
wherein
the first group of wordlines further comprises a pass wordline coupled to a gate of a pass transistor, wherein a drain node of the pass transistor is coupled to a common node connecting the first transistor with the first two-terminal memory cell and a source node of the pass transistor is coupled to a second common node connecting the second transistor with the second two-terminal memory cell, and wherein activation of the pass transistor by the pass wordline electrically couples the common node to the second common node through the pass transistor.

10 more elements

A method of fabricating a memory array of an integrated circuit, comprising:

forming a set of transistors in a diffusion layer of a substrate;
forming a set of resistive memory cells (ReMEM cells) at least in part overlying the set of transistors and the diffusion layer, wherein a first group of the ReMEM cells in a first portion of the set of ReMEM cells has a first intercell pitch and a second group of the ReMEM cells in a second portion of the set of ReMEM cells has a second intercell pitch equal to or substantially equal to the first intercell pitch;
coupling first terminals of a first group of the ReMEM cells to a bitline and respective second terminals of the first group of ReMEM cells to respective transistors of a first portion of the set of transistors;
configure the first group of the ReMEM cells for many-time program (MTP) or one-time program (OTP) operation;
couple a first terminal of a first ReMEM cell of a second group of the ReMEM cells to the bitline and a second terminal of the first ReMEM cell to a first transistor of a second portion of the set of transistors to form a first 1T1R memory circuit;
couple a first terminal of a second ReMEM cell of the second group of the ReMEM cells to the bitline and a second terminal of the second ReMEM cell to a second transistor of the second portion of the set of transistors to form a second 1T1R memory circuit;
and
configure the second group of the ReMEM cells for differential physical unclonable function (PUF) operation, further comprising:
couple the first ReMEM cell and the second ReMEM cell to a pass transistor, comprising coupling a drain node of the pass transistor to a common node connecting the first ReMEM cell to the first transistor of the first 1T1R memory circuit, and coupling a source node of the pass transistor to a second common node connecting the second ReMEM cell to the second transistor of the second 1T1R memory circuit, and
couple a pass wordline to a gate node of the pass transistor.

7 more elements

Dependencies are inferred from the claim text.