Non-volatile memory having first and second leday circuits, and electronic system and method

An electronic system comprising:

• a processor configured to generate an address signal;
• and
• a non-volatile memory operatively coupled to the processor and comprising:
• a memory area having a plurality of bit-lines and a plurality of word-lines;
• a current source configured to provide a programming current to one or more of the bit-lines, wherein the current source is supplied via a first supply voltage;
• a power supply circuit configured to generate a first voltage and a second voltage, wherein the second voltage is smaller than the first voltage, wherein the first voltage corresponds to or is smaller than the first supply voltage, and wherein the second voltage corresponds to or is greater than a second supply voltage;
• and
• a row decoder configured to connect one of the word-lines to ground as a first function of the address signal, and comprising a demultiplexer configured to provide enable signals, a respective enable signal for each word-line, and to assert one of the enable signals as a second function of the address signal, wherein the demultiplexer is supplied by the second supply voltage, wherein each enable signal is connected to either the second supply voltage or the ground, wherein the second supply voltage is smaller than the first supply voltage, and wherein the row decoder comprises for each word-line:
• a pull-up connected between the respective word-line and the first supply voltage;
• a first n-channel field-effect transistor (FET), wherein a source terminal of the first n-channel FET is connected to the ground, and a gate terminal of the first n-channel FET is connected to a first signal;
• a second n-channel FET, wherein a drain terminal of the second n-channel FET is connected to the respective word-line, a source terminal of the second n-channel FET is connected to a drain terminal of the first n-channel FET, and a gate terminal of the second n-channel FET is connected to the second voltage;
• a first p-channel FET, wherein a drain terminal of the first p-channel FET is connected to the second voltage, a source terminal of the first p-channel FET is connected to the respective word-line, and a gate terminal of the first p-channel FET is connected to a second signal;
• a bias circuit configured to set a drain voltage at the drain terminal of the first n-channel FET to the second voltage when the first n-channel FET and the second n-channel FET are opened;
• a first delay circuit configured to:
• detect changes in the respective enable signal;
• in response to detecting a change from an asserted logic level to a de-asserted logic level of the respective enable signal, connect the first signal to the ground;
• and
• in response to detecting a change from the de-asserted logic level to the asserted logic level of the respective enable signal, set the first signal after a first delay to a voltage in order to close the first FET;
• and
• a second delay circuit configured to:
• detect the changes in the respective enable signal;
• in response to detecting the change from the de-asserted logic level to the asserted logic level of the respective enable signal, set the second signal to the second voltage;
• and
• in response to detecting the change from the asserted logic level to the de-asserted logic level of the respective enable signal, set the second signal after a second delay to the first voltage.

A method of operating a non-volatile memory, the non-volatile memory comprising a memory area having a plurality of bit-lines and a plurality of word-lines, a current source being supplied via a first supply voltage, a power supply circuit configured to generate a first voltage and a second voltage, the second voltage being smaller than the first voltage, the first voltage corresponding to or being smaller than the first supply voltage, and the second voltage corresponding to or being greater than a second supply voltage, and a row decoder comprising a demultiplexer configured to provide enable signals, a respective enable signal for each word-line, and to assert one of the enable signals as a first function of an address signal, the demultiplexer being supplied by the second supply voltage, each enable signal being connected to either the second supply voltage or ground, and the row decoder comprising, for each word-line, a pull-up connected between the respective word-line and the first supply voltage, a first n-channel field-effect transistor (FET), a source terminal of the first n-channel FET being connected to the ground, and a gate terminal of the first n-channel FET is connected to a first signal, a second n-channel FET, a drain terminal of the second n-channel FET being connected to the respective word-line, a source terminal of the second n-channel FET is connected to a drain terminal of the first n-channel FET, and a gate terminal of the second n-channel FET is connected to the second voltage, a first p-channel FET, a drain terminal of the first p-channel FET being connected to the second voltage, a source terminal of the first p-channel FET is connected to the respective word-line, and a gate terminal of the first p-channel FET is connected to a second signal, a bias circuit, a first delay circuit, and a second delay circuit, the method comprising:

• providing the first supply voltage and the second supply voltage to the non-volatile memory, the second supply voltage being smaller than the first supply voltage;
• and
• providing the address signal to the row decoder.