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US 6,314,014 B1Granted
Programmable resistance memory arrays with reference cells
AssigneeOvonyx, Inc.
InventorsTyler Lowrey, Guy C. Wicker
Life of this patent
Estimating the term…
Abstract
A memory system comprising memory cells and reference cells each including a programmable resistance element. The resistance state of a memory cell is determined by comparing a sense signal developed by the memory cell with a reference signal developed by one or more of the reference cells. The programmable resistance elements may comprise a phase-change material.
Claims99
A memory system, comprising:
- one or more memory cells, each of said memory cells including a programmable resistor programmable to at least a first resistance state and a second resistance state;
- one or more reference cells, each of said reference cells including a programmable resistor programmable to at least said first resistance state and said second resistance state;
- and
- a comparison circuit in communication with said memory cells and with said reference cells, said comparison circuit adapted to compare at least one sense signal developed by at least one of said memory cells with at least one reference signal developed by at least one of said reference cells and to provide at least one output signal in response to said comparisons.
1 more element
A memory system, comprising:
- one or more memory cells, each of said memory cells including a programmable resistor programmable to at least a first resistance state and a second resistance state;
- one or more reference cells, each of said reference cells including a programmable resistor programmable to at least said first resistance state and said second resistance state;
- and
- a comparison circuit in communication with said memory cells and with said reference cells, said comparison circuit adapted to compare a sense signal developed by one of said memory cells with a reference signal developed by at least one of said reference cells and to provide an output signal in response to said comparison.
1 more element
A memory system, comprising:
- at least a first and a second memory array, each of said arrays comprising:
- one or more memory cells, each of said memory cells including a programmable resistor programmable to at least a first resistance state and a second resistance state;
- one or more reference cells, each of said reference cells including a programmable resistor programmable to at least said first resistance state and said second resistance state;
- and
- a comparison circuit in communication with said first and second arrays, said comparison circuit adapted to compare at least one sense signal developed by at least one of said memory cells of said first array with at least one reference signal developed by at least one of said reference cells of said second array, said comparison circuit adapted to compare at least one sense signal developed by at least one of said memory cells of said second array with at least one reference signal developed by at least one of said reference cells of said first array, said comparison circuit adapted to provide at least one output signal in response to said comparisons.
2 more elements
A memory system, comprising:
- a memory cell including a first programmable resistor programmable to at least a first resistance state and a second resistance state;
- a second programmable resistor programmable to at least said first resistance state and said second resistance state, said second resistor programmed to said first resistance state;
- third programmable resistor programmable to at least said first resistance state and said second resistance state, said third resistor programmed to said second resistance state;
- and
- a comparator adapted to compare a sense signal developed by said first programmable resistor with a reference signal developed by said second programmable resistor and/or said third programmable resistor.
2 more elements
A method of reading a memory cell, said memory cell including a programmable resistor programmable to at least a first resistance state and a second resistance state, said method comprising the steps of:
- providing one or more reference cells, each of said reference cells including a programmable resistor programmable to at least said first resistance state and said second resistance state;
- developing a sense signal by directing a current through the programmable resistor of said memory cell;
- developing at least one reference signal by directing at least one current through the programmable resistor of at least one of said reference cells;
- comparing said sense signal with said at least one reference signal;
- and
- providing an output signal in response to said comparing step.
3 more elements
A method of reading a memory cell, said memory cell comprising a programmable resistor programmable to at least a first resistance state and a second resistance state, said memory cell interconnecting a row line and a column line, said method comprising the steps of:
- directing said column line to a first voltage level;
- directing said row line to a second voltage level sufficient to cause a current to flow through said programmable resistor, said current directing said column line to a third voltage level;
- and
- comparing said third voltage level to a reference voltage, said reference voltage developed by directing at least one current through one or more reference cells, each of said reference cells comprising a programmable resistor programmable to at least said first resistance state and said second resistance state.
1 more element
A memory system comprising:
- a memory cell, said memory cell including a programmable resistor programmable to at least a first resistance state and a second resistance state;
- one or more reference cells, each of said reference cell programmable to at least said first resistance state and said second resistance state;
- and
- a comparison circuit in communication with said memory cell and said reference cells, said comparison circuit adapted to compare a sense signal developed by said memory cell with at least one reference signal developed by said reference cells and provide an output signal in response to said comparisons.
1 more element
Dependencies are inferred from the claim text.