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US 12,751,017 B2Granted
Memory circuit comprising electronic cells with ovonic threshold switching layers and a control circuit
AssigneeSTMicroelectronics International N.V.
InventorAndrea Redaelli
Life of this patent
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Abstract
Each electronic cell of a memory array includes an integrated stack having, successively, a first electrode, an intermediate layer formed by an ovonic threshold switching layer, and a resistor connected to the intermediate layer. A control circuit is connected to the electronic cell. The control circuit is structured and configured to apply, between the first electrode and the resistor, a first voltage impulse of a first polarity to set a first logic state of the electronic cell and a second voltage impulse of a second polarity, opposite the first polarity, to set a second logic state of the electronic cell.
Claims19
A memory circuit, comprising:
- a memory array comprising a plurality of electronic cells, wherein at least one electronic cell comprises an integrated stack having successively:
- i) a first electrode;
- ii) an intermediate layer consisting solely of an ovonic threshold switching layer;
- and
- iii) a resistor;
- wherein the ovonic threshold switching layer is in direct contact with the first electrode and is in direct contact with the resistor;
- wherein the memory array further includes a word line and a bit line, wherein one of the word line and bit line is connected to the first electrode and the other of the word line and bit line is connected to the resistor;
- and
- a control circuit connected to the at least one electronic cell through the word line and bit line, wherein the control circuit is configured to apply, between the first electrode and the resistor, a first voltage impulse of a first polarity to program the ovonic threshold switching layer of the electronic cell in a first logic state and apply a second voltage impulse of a second polarity, opposite the first polarity, to program the ovonic threshold switching layer of the electronic cell in a second logic state, different from the first logic state.
6 more elements
A memory circuit, comprising:
- a memory array comprising a plurality of electronic cells, wherein at least one electronic cell comprises an integrated stack having successively:
- i) a first electrode;
- ii) an intermediate layer consisting solely of an ovonic threshold switching layer;
- and
- iii) a resistor;
- wherein the ovonic threshold switching layer is in direct contact with the first electrode and is in direct contact with the resistor;
- and
- a transistor connected to the resistor on an opposite side with respect to the intermediate layer;
- wherein the memory array further includes a word line and a bit line, wherein one of the word line and bit line is connected to the first electrode and the other of the word line and bit line is connected to the transistor;
- and
- a control circuit connected to the at least one electronic cell through the word line and bit line, wherein the control circuit is configured to apply, between the first electrode and the resistor, a first voltage impulse of a first polarity to program the ovonic threshold switching layer of the electronic cell in a first logic state and apply a second voltage impulse of a second polarity, opposite the first polarity, to program the ovonic threshold switching layer of the electronic cell in set a second logic state, different from the first logic state.
8 more elements
A circuit, comprising:
- an ovonic threshold switching memory cell formed by an integrated stack consisting of a first electrode, a resistor, and an ovonic threshold switching layer having a first surface in direct contact with the first electrode and a second surface in direct contact with the resistor;
- a word line and a bit line, wherein one of the word line and bit line is connected to the first electrode and the other of the word line and bit line is connected to the transistor;
- and
- a control circuit electrically connected to the ovonic threshold switching memory cell and configured to program the ovonic threshold switching layer to set a first logic state by applying, between the first electrode and the resistor, a first voltage impulse of a first polarity and to program the ovonic threshold switching layer to a second logic state, different than the first logic state, by applying, between the first electrode and the resistor, a second voltage impulse of a second polarity opposite the first polarity.
1 more element
Dependencies are inferred from the claim text.