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US 6,462,984 B1Granted
Biasing scheme of floating unselected wordlines and bitlines of a diode-based memory array
AssigneeIntel Corporation
InventorsDaniel Xu, Tyler A. Lowrey, David L. Kencke
Life of this patent
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Abstract
An integrated circuit (IC) has a number of memory cells, each of which has a diode structure coupled between a bitline and a wordline that are selected when programming that cell. A target memory cell of the IC is programmed while simultaneously floating a number of unselected bitlines and wordlines in the IC.
Claims20
A method comprising:
- floating a plurality of unselected bitlines and a plurality of unselected wordlines of an integrated circuit (IC), the IC having a plurality of memory cells each of which has a diode structure coupled between a bitline and a wordline that are selected when programming that cell;
- and
- programming a target memory cell of the IC while simultaneously floating said plurality of unselected bitlines and said plurality of unselected wordlines.
A method comprising:
- providing each of a plurality of unselected bitlines and a plurality of unselected wordlines of an integrated circuit (IC) with high impedance to a power supply node and a power return node of the IC, the IC having a plurality of memory cells each of which has a diode structure coupled between a bitline and a wordline that are selected when programming that cell;
- and
- programming a target memory cell of the IC while simultaneously providing said high impedance to said plurality of unselected bitlines and said plurality of unselected wordlines.
An integrated circuit device comprising:
- a plurality of bitlines and a plurality of wordlines;
- a plurality of memory cells each of which has a diode structure coupled between a separate bitline-wordline pair of the plurality of bitlines and of the plurality of wordlines, the pair to be selected when programming that cell;
- and
- timing logic, pulse generation and drive circuitry coupled to the plurality of bitlines and wordlines, to program a target memory cell of the plurality of memory cells while simultaneously floating unselected ones of said plurality of bitlines and unselected ones of said plurality of wordlines.
1 more element
An integrated circuit device comprising:
- a plurality of bitlines and a plurality of wordlines;
- a plurality of memory cells each of which has a diode structure coupled between a separate bitline-wordline pair of the plurality of bitlines and of the plurality of wordlines, the pair to be selected when programming that cell;
- and
- timing logic, pulse generation and drive circuitry coupled to the plurality of bitlines and wordlines, to program a target memory cell of the plurality of memory cells while simultaneously causing unselected ones of said plurality of bitlines and unselected ones of said plurality of wordlines to have high impedance to a power supply node and a power return node of the device.
1 more element
Dependencies are inferred from the claim text.