G11C 11/4097
Bit-line organisation
Official title: Bit-line organisation, e.g. bit-line layout, folded bit lines
G11C11/4097 (Bit-line organisation) appears on 1,854 US grants and 1,709 published applications in this corpus.
Search patents in G11C- Granted patents
- 1,854
- Published applications
- 1,709
- Assignees
- 230
- Inventors
- 1,967
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 4 | 0 |
| 1978 | 6 | 0 |
| 1979 | 6 | 0 |
| 1980 | 2 | 0 |
| 1981 | 1 | 0 |
| 1982 | 3 | 0 |
| 1983 | 2 | 0 |
| 1984 | 5 | 0 |
| 1985 | 5 | 0 |
| 1986 | 7 | 0 |
| 1987 | 15 | 0 |
| 1988 | 9 | 0 |
| 1989 | 16 | 0 |
| 1990 | 17 | 0 |
| 1991 | 16 | 0 |
| 1992 | 13 | 0 |
| 1993 | 9 | 0 |
| 1994 | 14 | 0 |
| 1995 | 7 | 0 |
| 1996 | 9 | 0 |
| 1997 | 18 | 0 |
| 1998 | 32 | 0 |
| 1999 | 22 | 0 |
| 2000 | 39 | 0 |
| 2001 | 37 | 22 |
| 2002 | 57 | 51 |
| 2003 | 54 | 56 |
| 2004 | 60 | 63 |
| 2005 | 40 | 62 |
| 2006 | 56 | 52 |
| 2007 | 54 | 69 |
| 2008 | 47 | 69 |
| 2009 | 52 | 56 |
| 2010 | 56 | 51 |
| 2011 | 45 | 51 |
| 2012 | 42 | 52 |
| 2013 | 57 | 65 |
| 2014 | 67 | 56 |
| 2015 | 63 | 52 |
| 2016 | 45 | 30 |
| 2017 | 39 | 35 |
| 2018 | 39 | 52 |
| 2019 | 71 | 83 |
| 2020 | 87 | 74 |
| 2021 | 85 | 101 |
| 2022 | 80 | 119 |
| 2023 | 90 | 114 |
| 2024 | 116 | 96 |
| 2025 | 71 | 97 |
| 2026 | 67 | 81 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor device6 Oct 2026US 12,757,369 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Apparatuses and methods for simultaneous in data path compute operations22 Sep 2026US 12,743,206 B2
- Method of forming ferroelectric chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer25 Aug 2026US 12,717,479 B2Kepler Computing Inc.
- Memory device including sub-wordline driver located below memory cell array and word lines driven by sub-wordline driver25 Aug 2026US 12,718,867 B2Samsung Electronics Co., Ltd.
- Integrated memory comprising secondary access devices between digit lines and primary access devices25 Aug 2026US 12,720,721 B2Micron Technology, Inc.
- Semiconductor device8 Oct 2026US 2026/0311745 A1Semiconductor Energy Laboratory Co.Ltd.
- Memory devices24 Sep 2026US 2026/0290428 A1Micron Technology, Inc.
- 3d-dram with open digit line quilt layout24 Sep 2026US 2026/0290441 A1Micron Technology, Inc.
- Volatile memory device24 Sep 2026US 2026/0290442 A1Samsung Electronics Co., Ltd.
- Ternary content addressable memory (tcam) having variable size entries24 Sep 2026US 2026/0290455 A1NXP B. V.
Most cited
By later US patents
- Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines462US 6,166,942 AMicron Technology, Inc. · 2000
- DRAM having bidirectional global bit lines453US 5,367,488 AGoldstar Electron Co., Ltd. · 1994
- Dynamic memory with isolated digit lines445US 5,506,811 AMicron Technology, Inc. · 1996
- Datapath architecture for high area efficiency428US 7,054,178 B1Etron Technology, Inc. · 2006
- Fast, low power, write scheme for memory circuits using pulsed off isolation device423US 6,122,211 AMicron Technology, Inc. · 2000