Ternary content addressable memory (tcam) having variable size entries

An integrated circuit, comprising:

• a ternary content addressable memory (TCAM) having a plurality of lines and a plurality of entries, in which each entry is formed by at least two contiguous lines of the plurality of lines, wherein each line is configured to store a corresponding extension value which indicates whether or not the line extends to a next contiguous line in forming an entry of the TCAM;
• and
• input compare lanes coupled to receive N beats in a current clock cycle, wherein the N beats correspond to N portions of a look-up key presented for a search operation in the TCAM, N being an integer greater than or equal to two;
• wherein the TCAM comprises:
• storage circuitry configured to store a corresponding cumulative line match (CLM) bit for each line of the plurality of lines, wherein an asserted CLM bit indicates that an isolated line match for the line to which it corresponds has occurred in a previous clock cycle;
• and
• prerequisite determination circuitry for each line of the plurality of lines configured to, in response to an isolated line match of a current line in the TCAM with any one of the N beats and both a first condition and a second condition being met, indicate that the corresponding CLM bit for the current line is to be asserted in a subsequent clock cycle, wherein the first condition is met when one of N lines in the TCAM preceding the current line is indicated as not extended or its corresponding CLM bit is asserted and the second condition is met when all intervening lines between the one of the N preceding lines of the TCAM and the current line each have an isolated match with one of the N beats in the current clock cycle.