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US 12,718,867 B2Granted
Memory device including sub-wordline driver located below memory cell array and word lines driven by sub-wordline driver
AssigneeSamsung Electronics Co., Ltd.
InventorsSuhwan Choi, Younghun Seo, Sangyun Kim
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Abstract
A memory device includes a plurality of sub-array areas each including a plurality of memory cells, a plurality of contact areas located between the plurality of sub-array areas, a plurality of word lines each extending in a first direction to cross the plurality of sub-array areas and the plurality of contact areas, and a plurality of sub-word line drivers beneath the plurality of sub-array areas and configured to drive the plurality of word lines, wherein each of the plurality of contact areas comprises a plurality of contacts electrically connecting a corresponding word line, among the plurality of word lines, to a sub-word line driver.
Claims20
A memory device comprising:
- a plurality of sub-array areas each including a plurality of memory cells, the plurality of sub-array areas comprising a first sub-array area including a first plurality of memory cells and a second sub-array area spaced from the first sub-array area in a first direction and including a second plurality of memory cells;
- a plurality of contact areas located between the plurality of sub-array areas, the plurality of contact areas comprising a first contact area located between the first sub-array area and the second sub-array area in the first direction;
- a plurality of word lines each extending in the first direction to cross the plurality of sub-array areas and the plurality of contact areas, the plurality of word lines including a first word line extending in the first direction and crossing the first sub-array area, the first contact area, and the second sub-array area, and the plurality of word lines further including a second word line extending in the first direction and crossing the first sub-array area, the first contact area, and the second sub-array area;
- and
- a plurality of sub-word line drivers beneath the plurality of sub-array areas and configured to apply driving voltage to the plurality of word lines, the plurality of sub-word line drivers comprising a first sub-word line driver configured to apply driving voltage to the first word line and a second sub-word line driver configured to apply driving voltage to the second word line,
- wherein each of the plurality of contact areas comprises a plurality of contacts electrically connecting a corresponding word line, among the plurality of word lines, to a sub-word line driver, the plurality of contacts of the first contact area comprising a first contact connecting the first word line to the first sub-word line driver and a second contact connecting the second word line to the second sub-word line driver.
3 more elements
A memory device comprising:
- a memory cell area comprising a memory array including a plurality of memory cells;
- and
- a peripheral circuit area beneath the memory cell area and including a peripheral circuit,
- wherein the memory cell area further comprises:
- a plurality of sub-array areas each including the plurality of memory cells, the plurality of sub-array areas comprising a first sub-array area including a first subset of the plurality of memory cells and a second sub-array area spaced from the first sub-array area in a first direction and including a second subset of the plurality of memory cells;
- a plurality of contact areas located between the plurality of sub-array areas, the plurality of contact areas comprising a first contact area located between the first sub-array area and the second sub-array area in the first direction;
- and
- a plurality of word lines each extending in the first direction to cross the plurality of sub-array areas and the plurality of contact areas, the plurality of word lines comprising a first word line extending in the first direction and crossing the first sub-array area, the first contact area, and the second sub-array area, and the plurality of word lines further comprising a second word line extending in the first direction and crossing the first sub-array area, the first contact area, and the second sub-array area,
- wherein the plurality of contact areas includes a plurality of contacts electrically connecting the plurality of word lines to the peripheral circuit, the plurality of contacts including a first contact of the first contact area electrically connecting the first word line to the peripheral circuit and a second contact of the first contact area electrically connecting the second word line to the peripheral circuit, and
- wherein the peripheral circuit is configured to apply driving voltage to the first word line and the second word line of the plurality of word lines.
7 more elements
A memory device comprising:
- a plurality of sub-array areas each including a plurality of memory cells;
- a plurality of contact areas located between the plurality of sub-array areas;
- a plurality of word lines each extending in a first direction;
- and
- a plurality of sub-word line drivers beneath the plurality of sub-array areas and configured to apply driving voltage to the plurality of word lines,
- wherein each of the plurality of contact areas comprises a plurality of contacts electrically connecting a corresponding word line, among the plurality of word lines, to a sub-word line driver, and
- wherein each of the plurality of word lines is connected to at least two corresponding sub-word line drivers, among the plurality of sub-word line drivers, and is configured to receive driving voltage from the at least two corresponding sub-word line drivers.
4 more elements
Dependencies are inferred from the claim text.