Apparatuses and methods for simultaneous in data path compute operations

An apparatus, comprising:

• an array of memory cells;
• sensing circuitry selectably coupled to the array of memory cells;
• a plurality of first input/output (I/O) lines configured as a data path that couples the sensing circuitry to a compute unit, wherein the compute unit includes a plurality of logic stripes and is positioned within respective bank sections of the array of memory cells;
• and
• one or more controllers associated with the compute unit, wherein the one or more controllers are configured to cause a first transfer of first data from a first portion of the sensing circuitry to a first logic stripe of the plurality of logic stripes via the plurality of first I/O lines and a second transfer of second data from a second portion of the sensing circuitry to a second logic stripe of the plurality of logic stripes via the plurality of first I/O lines, wherein the first logic stripe performs a first number of operations comprising a first type of computation on the first data simultaneously with the second logic stripe performing a second number of operations comprising a second type of computation different from the first type of computation on the second data, wherein results of the first number of operations or the second number of operations, or both, are stored in the array of memory cells without enabling one or more second lines to transfer the results from the array of memory cells to circuitry external to the array of memory cells.

A method, comprising:

• transferring data from sensing circuitry selectably coupled to an array of memory cells to a compute unit via a plurality of first input/output (I/O) lines configured as a data path that couples the sensing circuitry to the compute unit, wherein the compute unit is positioned within respective bank sections of the array of memory cells;
• performing, during a first duration, a first number of operations comprising a first type of computation on a first portion of the data transferred from the sensing circuitry to the compute unit via the plurality of first I/O lines;
• performing, during the first duration and simultaneously with the first number of operations, a second number of operations comprising a second type of computation different from the first type of computation on a second portion of the data transferred from the sensing circuitry to the compute unit via the plurality of first I/O lines;
• and
• storing results of the first number of operations or the second number of operations, or both, in the array of memory cells without enabling one or more second lines to transfer the results from the array of memory cells to circuitry external to the array of memory cells.