US 12,757,369 B2Granted

Semiconductor device

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorJhon-Jhy Liaw

Life of this patent

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Abstract

Semiconductor devices are provided. A first memory cell includes a first pull-down transistor, a first pass-gate transistor, a first pull-up transistor, and a first isolation transistor. A second memory cell includes a second pull-down transistor, a second pass-gate transistor, a second pull-up transistor, and a second isolation transistor. The first and second isolation transistors share a common gate connected to a VDD line. The gates of the first and second pass-gate transistors are connected to a first WL landing pad and a second WL landing pad. The sources of the first and second pass-gate transistors are connected to the first and second bit lines. The VDD line, the first and second WL landing pads, and the first and second bit lines are formed in a first metal layer, and the VDD line, the first and second bit lines are longer than the first and second WL landing pads.

Claims20

Dependent claims

A semiconductor device, comprising:

a first memory cell, comprising:
a first pull-down transistor and a first pass-gate transistor formed over a first P-type well region in a substrate;
and
a first pull-up transistor and a first isolation transistor formed over an N-type well region in the substrate;
and
a second memory cell, comprising:
a second pull-down transistor and a second pass-gate transistor formed over a second P-type well region in the substrate;
and
a second pull-up transistor and a second isolation transistor formed over the N-type well region in the substrate,
wherein the first and second isolation transistors share a common gate extending in a first direction, and wherein the common gate is electrically connected to a VDD line extending in a second direction that is perpendicular to the first direction,
wherein gates of the first and second pass-gate transistors are electrically connected to a first word line (WL) landing pad and a second WL landing pad, respectively,
wherein sources of the first and second pass-gate transistors are electrically connected to a first bit line and a second bit line extending in the second direction, respectively, and
wherein the VDD line, the first WL landing pad, the second WL landing pad, the first bit line and the second bit line are formed in a first metal layer, and the first and second bit lines and the VDD line are longer than the first and second WL landing pads in the second direction.

10 more elements

A semiconductor device, comprising:

a first active region extending along a first direction and over a P-type well region in a substrate;
a second active region extending along the first direction and over an N-type well region in the substrate;
a first gate structure extending along a second direction and engaging the first active region to form a first transistor;
a second gate structure extending along the second direction and engaging the first active region and the second active region to form a second transistor and a third transistor, respectively;
a third gate structure extending along the second direction and engaging the first active region and the second active region to form a fourth transistor and a fifth transistor, respectively;
a fourth gate structure extending along the second direction and engaging the first active region to form a sixth transistor;
and
a fifth gate structure extending along the second direction and engaging the second active region to form a seventh transistor,
wherein the fifth gate structure is electrically connected to a first power line extending in the first direction, and the first gate structure is electrically connected to a first metal line landing pad,
wherein a source of the first transistor is electrically connected to a second metal line extending in the first direction through a second metal line landing pad and a third metal line landing pad,
wherein a source of the sixth transistor is electrically connected to a third metal line extending in the first direction, wherein the second metal line landing pad is disposed between the third metal line and the first metal line landing pad along the second direction, and
wherein the second and third metal lines are wider than the first power line and the first metal line landing pad.

9 more elements

A semiconductor device, comprising:

a first cell, comprising:
a first active region extending along a first direction and over a first P-type well region in a substrate;
a second active region extending along the first direction and over an N-type well region in the substrate;
a first gate structure extending along a second direction and engaging the first active region;
a second gate structure extending along the second direction and engaging the first active region and the second active region, such that the second gate structure is shared by the first active region and the second active region;
and
a first portion of a third gate structure engaging the second active region, wherein the third gate structure extends along the second direction;
and
a second cell adjacent to and in contact with the first cell, comprising:
a third active region extending in the first direction and formed over a second P-type well region in the substrate;
a fourth active region extending in the first direction formed over the N-type well region, wherein the N-type well region is disposed between the first and second P-type well regions;
a fourth gate structure extending along the second direction and engaging the third active region;
a fifth gate structure extending along the second direction and engaging the third active region and the fourth active region, such that the fifth gate structure is shared by the third active region and the fourth active region;
and
a second portion of the third gate structure engaging the fourth active region, such that the third gate structure is shared by the second active region and the fourth active region,
wherein the fourth gate structure is electrically connected to a first metal line landing pad extending in the first direction, and the first metal line landing pad is electrically connected to a first metal line extending in the second direction,
wherein the first metal line overlaps the second gate structure and the fifth gate structure, and
wherein the third gate structure is electrically connected to a first power line extending in the first direction, and the first power line is disposed between the second gate structure and the fifth gate structure, wherein the first direction is perpendicular to the second direction.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/779,402Filed 22 Jul 2024 · continuation
Priority: 29 Jun 2022
Published: US 2024/0008238 A114 Nov 2024
Granted: 6 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 11/4085
Address circuits: word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
G11C 11/4096
Read-write [R-W] circuits: input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Family

Application17/853,098Parent of this continuation · filed 29 Jun 2022
US 2024/0381606 A1Pre-grant publication · published 14 Nov 2024
US 12,089,391 B2Parent of this continuation
US 2024/0008238 A1Published application
US 12,757,369 B2This patent

From the US filing history. Foreign family members aren’t listed.