Memory devices

A volatile memory device, comprising:

• a first die comprising:
• a stack structure comprising:
• levels of insulative material;
• and
• levels of semiconductive material vertically alternating with the levels of insulative material;
• memory cells within the stack structure and individually comprising:
• a first transistor structure including a channel region comprising a portion of the semiconductive material;
• a second transistor structure horizontally neighboring the first transistor structure and including an additional channel region comprising an additional portion of the semiconductive material;
• and
• a capacitor coupled to the first transistor structure and the second transistor structure;
• digit line contact structures vertically extending through the stack structure and individually in electrical communication with the channel region and the additional channel region of respective ones of the memory cells;
• digit line structures vertically over the digit line contact structures and individually comprising:
• a first section horizontally extending in a first direction;
• and
• second sections integral with the first section and horizontally extending in a second direction orthogonal to the first direction, individual ones of the second sections in contact with individual ones of the digit line contact structures;
• decoupling capacitor structures horizontally offset from the memory cells and vertically overlapping the capacitor of respective ones of the memory cells;
• and
• a conductive plate structure horizontally extending between horizontally neighboring columns of the decoupling capacitor structures;
• and
• a second die bonded to the first die and comprising sense amplifier circuits vertically over the digit line structures.

A dynamic random access memory (DRAM) device, comprising:

• a first die comprising:
• memory cells individually comprising:
• a first transistor and a second transistor horizontally neighboring the first transistor, the first transistor and the second transistor individually comprising:
• channel region;
• and
• conductive word line structure vertically neighboring the channel region;
• a capacitor comprising:
• a first electrode coupled to the first transistor;
• and
• a second electrode coupled to the second transistor;
• and
• conductive routing structures vertically interposed between the capacitor and each of the first transistor and the second transistor;
• and
• digit line structures coupled to the first transistor and the second transistor of the memory cells;
• and
• a second die vertically overlying the first die and comprising sense amplifier circuitry operably connected to the digit line structures.