Y10S 257/909
Macrocell arrays
Official title: Macrocell arrays, e.g. gate arrays with variable size or configuration of cells
Y10S257/909 (Macrocell arrays) appears on 114 US grants and 38 published applications in this corpus.
Search patents in Y10S- Granted patents
- 114
- Published applications
- 38
- Assignees
- 72
- Inventors
- 174
- Latest grant
- 3 Mar 2015
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 3 | 0 |
| 1977 | 2 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 3 | 0 |
| 1981 | 2 | 0 |
| 1982 | 2 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 2 | 0 |
| 1987 | 2 | 0 |
| 1988 | 2 | 0 |
| 1989 | 2 | 0 |
| 1990 | 3 | 0 |
| 1991 | 4 | 0 |
| 1992 | 3 | 0 |
| 1993 | 2 | 0 |
| 1994 | 3 | 0 |
| 1995 | 3 | 0 |
| 1996 | 5 | 0 |
| 1997 | 6 | 0 |
| 1998 | 5 | 0 |
| 1999 | 5 | 0 |
| 2000 | 2 | 0 |
| 2001 | 5 | 1 |
| 2002 | 5 | 5 |
| 2003 | 6 | 5 |
| 2004 | 6 | 4 |
| 2005 | 5 | 7 |
| 2006 | 4 | 5 |
| 2007 | 3 | 2 |
| 2008 | 5 | 3 |
| 2009 | 3 | 1 |
| 2010 | 3 | 0 |
| 2011 | 1 | 4 |
| 2012 | 0 | 0 |
| 2013 | 0 | 0 |
| 2014 | 4 | 1 |
| 2015 | 1 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning3 Mar 2015US 8,969,923 B2SanDisk 3D LLC
- Semiconductor devices including SRAM cell and methods for fabricating the same14 Oct 2014US 8,860,096 B2Samsung Electronics Co., Ltd.
- Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning19 Aug 2014US 8,809,128 B2SanDisk 3D LLC
- Methods of forming pillars for memory cells using sequential sidewall patterning3 Jun 2014US 8,741,696 B2SanDisk 3D LLC
- Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning25 Mar 2014US 8,679,967 B2SanDisk 3D LLC
- Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning6 Nov 2014US 2014/0328105 A1SanDisk 3D LLC
- Semiconductor Devices Including SRAM Cell and Methods for Fabricating the Same6 Oct 2011US 2011/0241121 A1Samsung Electronics Co., Ltd.
- Methods of forming pillars for memory cells using sequential sidewall patterning28 Apr 2011US 2011/0095338 A1SanDisk 3D LLC
- Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning28 Apr 2011US 2011/0095434 A1SanDisk 3D LLC
- Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning28 Apr 2011US 2011/0095438 A1SanDisk 3D LLC
Most cited
By later US patents
- Method of making an adaptive configurable gate array305US 5,217,916 ATRW Inc. · 1993
- Integrated circuit cell architecture and routing scheme237US 5,923,059 AIn-Chip Systems, Inc. · 1999
- Integrated circuit cell architecture and routing scheme231US 5,898,194 AInChip Systems, Inc. · 1999
- Gate array core cell for VLSI ASIC devices206US 6,765,245 B2BAE Systems Information and Electronic Systems Integration Inc. · 2004
- Gate array cell architecture and routing scheme193US 5,723,883 AIn-Chip · 1998