US 8,969,923 B2Granted

Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning

AssigneeSanDisk 3D LLC

InventorsRoy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka

Life of this patent

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Abstract

Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.

Claims13

Dependent claims

A three-dimensional memory array comprising:

a memory array layer including an array and a plurality of memory lines wherein portions of the memory lines extend from the array substantially parallel to each other,
wherein a first subset of the memory lines extend from a first side of the array,
wherein a second subset of the memory lines extend from a second side of the array,
wherein within the first subset of memory lines a first plurality of memory lines terminate proximate an edge of the array,
wherein within the first subset of memory lines a second plurality of memory lines extend beyond the edge of the array into a contact region,
wherein the contact region includes a plurality of contacts adapted to couple the second plurality of memory lines to support circuitry,
wherein the contacts are disposed in two or more rows, the contact rows disposed substantially non-parallel to the memory lines, and
wherein adjacent memory lines couple to contacts in different rows.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/334,653Filed 17 Jul 2014 · division
Priority: 26 Oct 2009
Published: US 2014/0328105 A16 Nov 2014
Granted: 3 Mar 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 5/06
Details of stores covered by group G11C11/00: arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 63/84
Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g.…:…
H10D 88/00
Three-dimensional [3d] integrated devices
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts

Family

Application61/255,080Us provisional application · filed 26 Oct 2009
Application61/255,085Us provisional application · filed 26 Oct 2009
Application12/911,900Parent of this division · filed 26 Oct 2010
US 2014/0328105 A1Pre-grant publication · published 6 Nov 2014
US 8,809,128 B2Parent of this division
US 2011/0095438 A1Published application
US 8,969,923 B2This patent

From the US filing history. Foreign family members aren’t listed.