Integrated circuit cell architecture and routing scheme

A method of designing an integrated circuit using cells comprising:

• providing a plurality of substantially rectangular basic cells disposed in rows along a first direction, each one of said basic cells including a P-type diffusion region and an N-type diffusion region for transistor source and drain terminals, at least a first gate electrode region for transistor gate terminals, said at least first gate electrode region bridging between said P-type diffusion regions and said N-type diffusion regions in a second direction transverse to said first direction, and contact regions for making electrical contact to said diffusion regions and said gate electrode region;
• forming a macro cell by interconnecting adjacent basic cells and wherein interconnections internal to said macro cell are made using interconnect lines from a first conductive layer and a second conductive layer;
• selectively coupling input/output terminals of a plurality of said macro cells together via first, second and third groups of global interconnect lines;
• forming said first group of global interconnect lines from said first conductive layer and disposed along said first direction;
• forming said second group of global interconnect lines from said second conductive layer above said first conductive layer, and disposed along said first direction;
• and
• forming said third group of global interconnect lines from a third conductive layer above said second conductive layer, and disposed transverse to said first direction along said second direction.