Semiconductor devices including SRAM cell and methods for fabricating the same

A semiconductor device including an SRAM cell, said SRAM cell comprising:

• a first load transistor, a first driver transistor and a first access transistor on a substrate, each of said first load, first driver, and first access transistors having a first source/drain and a second source/drain, wherein said first source/drains are connected to a first node;
• a power line, a first ground line and a first bit line respectively connected to said second source/drains of said first load, first driver and first access transistors, wherein the power line, the first ground line and the first bit line are disposed at substantially a same level to extend in a first direction;
• a word line connected to a gate of the first access transistor that extends in a second direction perpendicular to the first direction, wherein the word line is disposed at a level that differs from that of the power line, the first ground line and the first bit line;
• a first interlayer dielectric layer on the first load transistor, the first driver transistor and the first access transistor;
• a second interlayer dielectric layer disposed on the first interlayer dielectric layer;
• a first power landing plug, a first ground landing plug and a first bit landing respectively connected through the first interlayer dielectric layer to the second source/drain of the first load transistor, the second source/drain of the first driver transistor and the second source/drain of the first access transistor;
• and
• a first power via plug, a first ground via plug and a first bit via plug respectively connected through the second interlayer dielectric layer to the first power landing plug, the first ground landing plug and the first bit landing plug,
• wherein the word line is disposed between the first interlayer dielectric layer and the second interlayer dielectric layer,
• the power line, the first ground line and the first bit line are disposed on the second interlayer dielectric layer,
• the first power via plug, the first ground via plug and the first bit via plug are respectively connected to the power line, the first ground line and the first bit line, and
• bottom surfaces of the first power via plug, the first ground via plug and the first bit via plug are narrower than top surfaces of the first power landing plug, the first ground landing plug and the first bit landing plug, respectively.