Gate array core cell for VLSI ASIC devices

A gate array core cell comprising:

• a plurality of P+ diffusion regions formed in a N-well region, wherein at least some of the P+ diffusion regions are separated from other P+ diffusion regions by a silicon oxide layer;
• a plurality of PMOS transistors of identical dimensions which are formed in at least some of the P+ diffusion regions;
• a plurality of N+ diffusion regions formed on a p-type of wafer/chip substrate wherein said N+ diffusion regions are each separated from at least one of said other N+ diffusion regions by a silicon oxide layer;
• and
• a plurality of NMOS transistors of substantially identical dimensions which are formed in each of said N+ diffusion regions, wherein the core cell is divided into isolated N+ and P+ diffusion regions so that there is no need for diffusion isolation transistors and the core cell includes PMOS transistor gate electrodes and there is pre-wiring of some of said PMOS transistor gate electrodes to a NMOS transistor gate electrodes at polysilicon level, which is the same level used to form the gate electrodes and pre-wiring of said PMOS to NMOS transistors.

A gate array core cell comprising

• a plurality of P+ diffusion regions formed in a N-well region, wherein at least some of the P+ diffusion regions are separated from other P+ diffusion regions by a silicon oxide layer;
• a plurality of PMOS transistors of identical dimensions which are formed in at least some of the P+ regions;
• a plurality of N+ diffusion regions formed on a p-type of wafer/chip substrate wherein said N+ diffusion regions are each separated from at least one of said other N+ diffusion regions by a silicon oxide layer;
• and
• a plurality of NMOS transistors of substantially identical dimensions which are formed in each of said N+ diffusion regions wherein the core cell is not connected to the PMOS and NMOS transistors that can be used as pass transistors or for forming logical circuit functions.

A gate array cell comprising:

• a plurality of P+ diffusion regions formed in a N-well region, wherein at least some of the P+ diffusion regions are separated from other P+ diffusion regions by a silicon oxide layer;
• a plurality of PMOS transistors of identical dimensions which are formed in at least some of the P+ diffusion regions;
• a plurality of N+ diffusion regions formed on a p-type of wafer/chip substrate wherein said N+ diffusion regions are each separated from at least one of said other N+ diffusion regions by a silicon oxide layer;
• and
• a plurality of NMOS transistors of substantially identical dimensions which are formed in each of said N+ diffusion regions wherein the core cell provides pre-placed polysilicon or local interconnect wires and said pre-placed wires are used to complete interconnections of different types of circuit functions whereby the use of said wires saves the need for metal wires and reduces cell size for higher circuit density.