Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning
AssigneeSanDisk 3D LLC
InventorsRoy E. Scheuerlein, Yoichiro Tanaka
Life of this patent
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Abstract
The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
Claims20
A method of forming a wiring pattern for a memory, comprising:
- forming first features from a first template layer disposed above a substrate;
- forming sidewall spacers adjacent the first features;
- forming second features in a second template layer by using the sidewall spacers as a hardmask;
- forming conductor features by depositing electrically conductive material on sidewalls of the second features;
- depositing a dielectric gap fill material over the conductor features;
- and
- planarizing the dielectric gap fill material so as to level the conductor features and form the wiring pattern.
Dependencies are inferred from the claim text.