Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning

A three-dimensional memory comprising:

• a plurality of memory layers coupled together by a plurality of zias, each zia including a zia contact area on at least one memory layer,
• wherein each memory layer includes one or more memory array blocks coupled to memory lines,
• wherein the memory lines extend from the memory array blocks,
• wherein the memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines,
• wherein the zia contact areas have a dimension larger than the nominal minimum feature size capability of the lithography tool, and
• wherein the memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas.

A memory layer for a three-dimensional memory, the memory layer comprising:

• one or more memory array blocks;
• a plurality of memory lines coupled to the memory array blocks;
• and
• a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory,
• wherein the memory lines extend from the memory array blocks,
• wherein the memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines,
• wherein the zia contact areas have a dimension larger than the nominal minimum feature size capability of the lithography tool, and
• wherein the memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas.

A memory layer for a three-dimensional memory, the memory layer comprising:

• a plurality of memory array blocks;
• a plurality of memory lines coupled to the memory array blocks;
• and
• a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory,
• wherein the memory lines extend from the memory array blocks and are formed using a sidewall defined process,
• wherein the memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines,
• wherein the zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines, and
• wherein the memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas.