Integrated circuit cell architecture and routing scheme

A basic cell for arrangement in rows for use in an integrated circuit using cells comprising:

• a P-type active diffusion region having a non-rectangular outline;
• an N-type active diffusion region having a non-rectangular outline;
• a first gate electrode extending across said P-type and N-type active diffusion regions in a first direction separating source contact regions and drain contact regions of a first PMOS transistor and separating source contact regions and drain contact regions of a first NMOS transistor, respectively;
• a second gate electrode extending across said P-type and N-type active diffusion regions in said first direction separating source contact regions and drain contact regions of a second PMOS transistor and separating source contact regions and drain contact regions of a second NMOS transistor, respectively, said first gate electrode having a first end and an opposing second end, said first end having a contact region laterally adjacent said P-type active diffusion region, said second end having no contact region, said first gate electrode having contact at an intermediate contact region, and said second gate electrode having a third end and an opposing fourth end, said third end having a contact region laterally adjacent said N-type active diffusion region, said fourth end having no contact region, said second gate electrode having contact at an intermediate contact region.

An integrated circuit using cells comprising:

• a first group of global interconnect lines made from a first conductive layer and disposed along a first direction;
• a second group of global interconnect lines made from a second conductive layer above said first conductive layer, and disposed along said first direction;
• a third group of global interconnect lines made from a third conductive layer above said second conductive layer, and disposed along a second direction substantially different than said first direction;
• and
• a plurality of basic cells, each one including diffusion regions for transistor source and drain terminals, gate electrode regions for transistor gate terminals, and contact regions for making electrical contact to said diffusion and gate electrode regions,
• wherein, a macro cell is made by interconnecting adjacent basic cells, and interconnections internal to a macro cell are made using interconnect lines from said first and second conductive layers, and
• wherein, said plurality of macro cells are selectively coupled together via said first, second and third group of global interconnect lines,
• wherein each one of said plurality of basic cells comprises a first diffusion region of a first type and a second diffusion region of a second type, and wherein said first and second diffusion regions are laid out in a non-rectangular shape,
• wherein each of said plurality of basic cells comprises a first and second gate electrode regions, each one of which is shared between a transistor made in said first diffusion region and a transistor made in said second diffusion region,
• wherein each of said plurality of basic cells has a substantially rectangular shape with a first and second substrate contact regions disposed in corners, and
• wherein said substantially rectangular shape of each of said plurality of basic cells has a first dimension defined by a maximum of nine interconnect lines made from said first conductive layer disposed in parallel in said first direction, and a second dimension defined by at least three interconnect lines made from said third conductive layer disposed in parallel in said second direction.

A circuit block for use in an integrated circuit constructed of circuit blocks comprising:

• a P-type diffusion region and an N-type diffusion region for transistor source and drain terminals oriented in parallel along a first direction, at least a first gate electrode region for transistor gate terminals, said at least first gate electrode region bridging between said P-type diffusion regions and said N-type diffusion regions in a second direction transverse to said first direction, and contact regions for making electrical contact to said diffusion regions and said gate electrode region;
• wherein a macro cell is formed by interconnecting adjacent transistors and wherein interconnections internal to said macro cell are made using interconnect lines from a first conductive layer;
• wherein input/output terminals of a plurality of said macro cells are selectively coupled together via first, second and third groups of global interconnect lines;
• said first group of global interconnect lines being formed from said first conductive layer and disposed along said first direction;
• said second group of global interconnect lines being formed from said second conductive layer above said first conductive layer, and disposed along said first direction;
• and
• said third group of global interconnect lines being formed from a third conductive layer above said second conductive layer, and disposed transverse to said first direction along said second direction.