H10W 72/245
Of outermost layers of multilayered bumps
Official title: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core}
H10W72/245 (Of outermost layers of multilayered bumps) appears on 674 US grants and 806 published applications in this corpus.
Search patents in H10W- Granted patents
- 674
- Published applications
- 806
- Assignees
- 238
- Inventors
- 1,256
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 1 | 0 |
| 1996 | 2 | 0 |
| 1997 | 0 | 0 |
| 1998 | 3 | 0 |
| 1999 | 4 | 0 |
| 2000 | 3 | 0 |
| 2001 | 4 | 1 |
| 2002 | 2 | 8 |
| 2003 | 4 | 5 |
| 2004 | 4 | 11 |
| 2005 | 9 | 11 |
| 2006 | 7 | 13 |
| 2007 | 7 | 10 |
| 2008 | 12 | 20 |
| 2009 | 9 | 21 |
| 2010 | 19 | 22 |
| 2011 | 22 | 43 |
| 2012 | 20 | 46 |
| 2013 | 42 | 59 |
| 2014 | 40 | 64 |
| 2015 | 51 | 75 |
| 2016 | 61 | 57 |
| 2017 | 69 | 62 |
| 2018 | 60 | 44 |
| 2019 | 46 | 41 |
| 2020 | 32 | 45 |
| 2021 | 32 | 32 |
| 2022 | 34 | 35 |
| 2023 | 29 | 24 |
| 2024 | 17 | 24 |
| 2025 | 19 | 22 |
| 2026 | 6 | 11 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Semiconductor package12 May 2026US 12,628,668 B2Samsung Electronics Co., Ltd.
- Half-buried electrical connection insert rod device28 Apr 2026US 12,616,054 B2Commissariat A L' Energie Atomique Et Aux Energies Alternatives
- Electronic device21 Apr 2026US 12,609,507 B2Sony Semiconductor Solutions Corporation
- Flip chip bonding method and chip used therein24 Mar 2026US 12,588,541 B2Chipbond Technology Corporation
- Semiconductor package3 Sep 2026US 2026/0262512 A1Samsung Electronics Co., Ltd.
- Diffusion soldering method and solder material20 Aug 2026US 2026/0241495 A1Infineon Technologies AG
- Joining layer and joining structure20 Aug 2026US 2026/0248015 A1TDK Corporation
- Electronic device6 Aug 2026US 2026/0229838 A1Sony Semiconductor Solutions Corporation
- Methods for low temperature bonding using nanoparticles30 Jul 2026US 2026/0223715 A1Adeia Semiconductor Technologies LLC
Most cited
By later US patents
- Method of making microelectronic spring contact elements226US 6,184,053 B2FormFactor, Inc. · 2001
- Three-dimensional (3D) integrated circuit with enhanced copper-to-copper bonding214US 8,546,956 B2International Business Machines Corporation · 2013
- Structures and methods for low temperature bonding using nanoparticles162US 10,892,246 B2Invensas Corporation · 2021
- Transfer wafer level packaging142US 6,727,576 B2Infineon Technologies AG · 2004
- Wafer level package using stud bump coated with solder135US 8,071,470 B2Carsem (M) Sdn. Bhd. · 2011