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US 12,628,668 B2Granted
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorMyungsam Kang
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a connection substrate with a cavity, a first semiconductor chip and a second semiconductor chip on the connection substrate, a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip being on the third semiconductor chip and being connected to each other through the third semiconductor chip, and a molding layer that covers the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, wherein the third semiconductor chip includes first bumps that are exposed through the molding layer and are connected to the first semiconductor chip and the second semiconductor chip.
Claims20
A semiconductor package, comprising:
- a connection substrate with a cavity;
- a first semiconductor chip and a second semiconductor chip each mounted on the connection substrate;
- a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip each having a portion vertically overlapping the third semiconductor chip and being connected to each other through the third semiconductor chip;
- and
- a molding layer that covers an upper surface of the third semiconductor chip and an upper surface of the connection substrate, the molding layer being disposed below the first semiconductor chip and the second semiconductor chip,
- wherein the third semiconductor chip includes first bumps that penetrate through and protrude from the molding layer, a first set of the first bumps being connected to the first semiconductor chip and a second set of the first bumps being connected to the second semiconductor chip.
3 more elements
A semiconductor package, comprising:
- a connection substrate with a cavity;
- a first semiconductor chip and a second semiconductor chip mounted on the connection substrate;
- a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip each having a chip portion vertically overlapping the third semiconductor chip and being connected to each other through the third semiconductor chip;
- and
- a molding layer that covers an upper surface of the third semiconductor chip and an upper surface of the connection substrate, the molding layer being disposed below the first semiconductor chip and the second semiconductor chip,
- wherein the third semiconductor chip includes first bumps that penetrate through and protrude from the molding layer, a first set of the first bumps being connected to the first semiconductor chip and a second set of the first bumps being connected to the second semiconductor chip, and
- wherein the connection substrate includes second bumps that penetrate through and protrude from the molding layer, a first set of the second bumps being connected to the first semiconductor chip and a second set of the second bumps being connected to the second semiconductor chip.
4 more elements
A semiconductor package, comprising:
- a connection substrate with a cavity;
- a first semiconductor chip and a second semiconductor chip on the connection substrate and having a portion vertically overlapping the cavity;
- a third semiconductor chip in the cavity of the connection substrate;
- and
- a molding layer between the third semiconductor chip and the connection substrate, the molding layer surrounding the third semiconductor chip and a top surface of the connection substrate,
- wherein the first semiconductor chip is mounted on the molding layer and is adjacent to a first side of the connection substrate, the first semiconductor chip being connected to the connection substrate and the third semiconductor chip,
- wherein the second semiconductor chip is mounted on the molding layer and is adjacent to a second side of the connection substrate, the second semiconductor chip being connected to the connection substrate and the third semiconductor chip,
- wherein the third semiconductor chip includes:
- first bumps protruding from a top surface of the third semiconductor chip to penetrate through and extend from the molding layer, a first set of the first bumps connected to a bottom surface of the first semiconductor chip and a second set of the first bumps connected to a bottom surface of the second semiconductor chip, and
- a first oxidation barrier layer that covers a surface of each of the first bumps, wherein the connection substrate includes:
- second bumps protruding from the top surface of the connection substrate to penetrate through and extend from the molding layer, a first set of the second bumps connected to the bottom surface of the first semiconductor chip and a second set of the second bumps connected to the bottom surface of the second semiconductor chip, and
- a second oxidation barrier layer that covers a surface of each of the second bumps,
- wherein the third semiconductor chip has the same thickness as the thickness of the connection substrate,
- wherein each of the first bumps and each of the second bumps has the same vertical length,
- wherein a diameter of each of the first bumps is in a range of about 10 μm to about 40 μm, and
- wherein a diameter of each of the second bumps is in a range of about 50 μm to about 100 μm.
13 more elements
Dependencies are inferred from the claim text.