Electronic device
AssigneeSony Semiconductor Solutions Corporation
InventorsTakashi IMAHIGASHI, Tsuyoshi ASAKAWA
Life of this patent
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Abstract
Please replace the currently pending Abstract with the following amended Abstract: An electronic device according to the present disclosure includes a semiconductor substrate a chip, and a bump. The chip has a thermal expansion coefficient different from that of the semiconductor substrate The bump connects the connection pads provided on the opposing principal surfaces of the semiconductor substrate and the chip. The bump has a porous metal layer and a metal film, The metal film is provided on at least one of a portion between the connection pad provided on the semiconductor substrate and the porous metal layer and a portion between the connection pad provided on the chip and the porous metal layer, and on the side surfaces of the porous metal layer.
Claims21
-8. (canceled)
A device, comprising:
- a substrate;
- and
- a bump provided on a surface of a connection pad provided on a principal surface of the substrate,
- wherein the bump includes:
- a porous metal layer;
- and
- a metal film provided between the porous metal layer and the connection pad and on side surfaces of the porous metal layer.
A device, comprising:
- a chip;
- and
- a bump provided on a surface of a connection pad provided on a principal surface of the chip,
- wherein the bump includes:
- a porous metal layer;
- and
- a metal film provided between the porous metal layer and the connection pad and on side surfaces of the porous metal layer.
A device, comprising:
- a substrate;
- a chip having a thermal expansion coefficient different from the substrate;
- and
- a bump that connects connection pads provided on opposing principle surfaces of the substrate and the chip,
- wherein the bump includes:
- a porous metal layer;
- and
- a metal film provided on at least one of a portion between the connection pad provided on the substrate and the porous metal layer and a portion between the connection pad provided on the chip and the porous metal layer, and on side surfaces of the porous metal layer.
Dependencies are inferred from the claim text.