Three-dimensional (3D) integrated circuit with enhanced copper-to-copper bonding
AssigneeInternational Business Machines Corporation
InventorSon V. Nguyen
Life of this patent
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Abstract
At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device wafer and on the at least one metal adhesion layer. The first and second device wafers are then bonded together. The bonding includes heating the devices wafers to a temperature of less than 400° C., with or without, application of an external applied pressure. During the heating, the two Cu surfaces are bonded together and the at least one metal adhesion layer gets oxygen atoms from the two Cu surfaces and forms at least one metal oxide bonding layer between the Cu surfaces.
Claims17
A three-dimensional (3D) integrated circuit comprising:
- a vertical stack of a first device wafer comprising a Cu surface and a second device wafer comprising another Cu surface, wherein a metal oxide bonding layer is located between the first Cu surface of the first device wafer and the another Cu surface of the second device wafer.
Dependencies are inferred from the claim text.