H10W 72/01235
By plating
Official title: {by plating, e.g. electroless plating or electroplating}
H10W72/01235 (By plating) appears on 2,484 US grants and 2,986 published applications in this corpus.
Search patents in H10W- Granted patents
- 2,484
- Published applications
- 2,986
- Assignees
- 426
- Inventors
- 3,471
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1995 | 2 | 0 |
| 1996 | 2 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 1 | 0 |
| 2000 | 4 | 0 |
| 2001 | 7 | 3 |
| 2002 | 10 | 7 |
| 2003 | 5 | 9 |
| 2004 | 10 | 14 |
| 2005 | 6 | 26 |
| 2006 | 9 | 25 |
| 2007 | 11 | 20 |
| 2008 | 14 | 43 |
| 2009 | 19 | 29 |
| 2010 | 25 | 45 |
| 2011 | 33 | 98 |
| 2012 | 58 | 168 |
| 2013 | 102 | 200 |
| 2014 | 150 | 201 |
| 2015 | 197 | 234 |
| 2016 | 209 | 193 |
| 2017 | 232 | 227 |
| 2018 | 198 | 176 |
| 2019 | 192 | 239 |
| 2020 | 201 | 228 |
| 2021 | 169 | 215 |
| 2022 | 185 | 167 |
| 2023 | 147 | 114 |
| 2024 | 138 | 126 |
| 2025 | 102 | 117 |
| 2026 | 44 | 62 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Sintered metal flip chip joints18 Aug 2026US 12,713,938 B2Texas Instruments Incorporated
- Thick redistribution layer features11 Aug 2026US 12,707,653 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device11 Aug 2026US 12,707,942 B2Samsung Electronics Co., Ltd.
- Integrated circuit having a routable leadframe11 Aug 2026US 12,707,986 B2Texas Instruments Incorporated
- Wiring substrate8 Oct 2026US 2026/0309912 A1Ibiden Co., Ltd.
- Semiconductor packages with separately plated metal pillars1 Oct 2026US 2026/0305410 A1Texas Instruments Incorporated
- Semiconductor structure and fabrication method thereof1 Oct 2026US 2026/0305439 A1United Microelectronics Corp.
- Multi-layer metal stack for wire bonding1 Oct 2026US 2026/0305453 A1
- Co-integration of Airbridges and 3D Integration Modules24 Sep 2026US 2026/0293678 A1
Most cited
By later US patents
- Testing of semiconductor chips with microbumps1,870US 9,372,206 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- 3DIC stacking device and method of manufacture962US 9,443,783 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Wafer scale packaging scheme253US 6,103,552 A2000
- Method of making microelectronic spring contact elements226US 6,184,053 B2FormFactor, Inc. · 2001
- Bump structure, bump forming method and package connecting body200US 6,229,220 B1International Business Machines Corporation · 2001