H10P 90/124
By processing the backside of the wafers
Official title: {by processing the backside of the wafers}
H10P90/124 (By processing the backside of the wafers) appears on 123 US grants and 161 published applications in this corpus.
Search patents in H10P- Granted patents
- 123
- Published applications
- 161
- Assignees
- 69
- Inventors
- 378
- Latest grant
- 1 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 2 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 1 |
| 2004 | 1 | 3 |
| 2005 | 0 | 3 |
| 2006 | 2 | 1 |
| 2007 | 1 | 1 |
| 2008 | 1 | 0 |
| 2009 | 0 | 0 |
| 2010 | 1 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 1 |
| 2013 | 0 | 3 |
| 2014 | 2 | 7 |
| 2015 | 8 | 9 |
| 2016 | 4 | 5 |
| 2017 | 9 | 11 |
| 2018 | 9 | 14 |
| 2019 | 10 | 10 |
| 2020 | 13 | 18 |
| 2021 | 15 | 12 |
| 2022 | 5 | 9 |
| 2023 | 7 | 14 |
| 2024 | 10 | 15 |
| 2025 | 9 | 13 |
| 2026 | 10 | 11 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Processing method of wafer1 Sep 2026US 12,727,445 B2Disco Corporation
- Method, apparatus, and system for wafer grounding28 Jul 2026US 12,696,725 B2ASML Netherlands B. V.
- Method for wafer backside polishing26 May 2026US 12,636,749 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method for manufacturing semiconductor silicon wafer composed of silicon wafer substrate and silicon monocrystalline epitaxial layer5 May 2026US 12,622,185 B2Globalwafers Japan Co., Ltd.
- Semiconductor device and manufacturing method thereof14 Apr 2026US 12,604,711 B2Nanya Technology Corporation
- Bow compensation of semiconductor substrate using plasma jet24 Sep 2026US 2026/0293619 A1Lam Research Corporation
- Method for manufacturing epitaxial wafer24 Sep 2026US 2026/0293620 A1Kabushiki Kaisha Toshiba
- Carrier structure and methods of forming the same20 Aug 2026US 2026/0248043 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Systems and methods for porous backside contacts16 Jul 2026US 2026/0206313 A1IQE plc
- Wafer-processing sheet and method for manufacturing a semiconductor device2 Jul 2026US 2026/0190943 A1Disco Corporation
Most cited
By later US patents
- Method of manufacturing a semiconductor device including removing a relief layer from back surface of semiconductor chip229US 9,646,856 B2Intel Deutschland GmbH · 2017
- Chip with encapsulated sides and exposed surface125US 9,064,883 B2Intel Mobile Communications GmbH · 2015
- Substrate thinning including planarization38US 7,064,069 B2Micron Technology, Inc. · 2006
- Laser, plasma etch, and backside grind process for wafer dicing27US 8,845,854 B2APPLIED Materials.Inc. · 2014
- Wafer processing method and method of manufacturing semiconductor device by using the same19US 9,070,729 B2Samsung Electronics Co., Ltd. · 2015