H10P 76/405
Characterised by their composition
Official title: {characterised by their composition, e.g. multilayer masks}
H10P76/405 (Characterised by their composition) appears on 2,292 US grants and 2,588 published applications in this corpus.
Search patents in H10P- Granted patents
- 2,292
- Published applications
- 2,588
- Assignees
- 365
- Inventors
- 4,292
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 3 | 0 |
| 1981 | 4 | 0 |
| 1982 | 5 | 0 |
| 1983 | 4 | 0 |
| 1984 | 0 | 0 |
| 1985 | 2 | 0 |
| 1986 | 4 | 0 |
| 1987 | 3 | 0 |
| 1988 | 1 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 2 | 0 |
| 1994 | 4 | 0 |
| 1995 | 5 | 0 |
| 1996 | 0 | 0 |
| 1997 | 2 | 0 |
| 1998 | 10 | 0 |
| 1999 | 11 | 0 |
| 2000 | 27 | 0 |
| 2001 | 46 | 17 |
| 2002 | 31 | 40 |
| 2003 | 27 | 35 |
| 2004 | 38 | 47 |
| 2005 | 27 | 51 |
| 2006 | 46 | 50 |
| 2007 | 28 | 37 |
| 2008 | 34 | 44 |
| 2009 | 31 | 38 |
| 2010 | 25 | 23 |
| 2011 | 33 | 22 |
| 2012 | 20 | 28 |
| 2013 | 30 | 40 |
| 2014 | 33 | 59 |
| 2015 | 71 | 132 |
| 2016 | 120 | 152 |
| 2017 | 152 | 181 |
| 2018 | 192 | 192 |
| 2019 | 179 | 220 |
| 2020 | 210 | 242 |
| 2021 | 181 | 203 |
| 2022 | 153 | 191 |
| 2023 | 123 | 148 |
| 2024 | 146 | 168 |
| 2025 | 133 | 141 |
| 2026 | 89 | 87 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method of manufacturing a vertical semiconductor memory device using metal mask layers6 Oct 2026US 12,757,689 B2Kioxia Corporation
- Method of manufacturing memory device using self-aligned double patterning (SADP)6 Oct 2026US 12,757,690 B2Nanya Technology Corporation
- Method for fabricating semiconductor device29 Sep 2026US 12,751,222 B2Samsung Electronics Co., Ltd.
- Treatment to control deposition rate29 Sep 2026US 12,751,223 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Methods and structures for improving etch profile of underlying layers22 Sep 2026US 12,745,612 B2Tokyo Electron Limited
- Structure and Method for Deep Trench Capacitor with Reduced Deformation1 Oct 2026US 2026/0304797 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method for fabricating nmos high-k metal gate and pmos high-k metal gate1 Oct 2026US 2026/0304883 A1Huahong Integrated Circuit(Chengdu) Corporation
- Method for manufacturing semiconductor device1 Oct 2026US 2026/0305267 A1Mitsubishi Electric Corporation
- Method of forming pattern and method of manufacturing semiconductor device1 Oct 2026US 2026/0305268 A1Samsung Electronics Co., Ltd.
- Doped underlayer suitable for extreme ultraviolet radiation dose reduction1 Oct 2026US 2026/0305269 A1ASM IP Holding B. V.
Most cited
By later US patents
- Method of spacer patterning to form a target integrated circuit pattern3,272US 9,576,814 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2017
- Method for integrated circuit patterning805US 9,184,054 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Frequency doubling using spacer mask774US 7,807,578 B2APPLIED Materials.Inc. · 2010
- Semiconductor substrate process using a low temperature deposited carbon-containing hard mask566US 7,323,401 B2APPLIED Materials.Inc. · 2008
- Pulsed PECVD method for modulating hydrogen content in hard mask545US 7,381,644 B1Novellus Systems, Inc. · 2008