H10D 64/021
Using multiple gate spacer layers
Official title: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
H10D64/021 (Using multiple gate spacer layers) appears on 5,849 US grants and 6,659 published applications in this corpus.
Search patents in H10D- Granted patents
- 5,849
- Published applications
- 6,659
- Assignees
- 421
- Inventors
- 6,586
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 2 | 0 |
| 1988 | 6 | 0 |
| 1989 | 6 | 0 |
| 1990 | 6 | 0 |
| 1991 | 7 | 0 |
| 1992 | 13 | 0 |
| 1993 | 10 | 0 |
| 1994 | 7 | 0 |
| 1995 | 11 | 0 |
| 1996 | 16 | 0 |
| 1997 | 26 | 0 |
| 1998 | 37 | 0 |
| 1999 | 52 | 0 |
| 2000 | 63 | 0 |
| 2001 | 66 | 17 |
| 2002 | 74 | 68 |
| 2003 | 97 | 109 |
| 2004 | 118 | 155 |
| 2005 | 130 | 250 |
| 2006 | 135 | 218 |
| 2007 | 124 | 235 |
| 2008 | 143 | 241 |
| 2009 | 133 | 155 |
| 2010 | 148 | 110 |
| 2011 | 116 | 128 |
| 2012 | 125 | 136 |
| 2013 | 123 | 134 |
| 2014 | 158 | 145 |
| 2015 | 178 | 265 |
| 2016 | 322 | 348 |
| 2017 | 356 | 378 |
| 2018 | 366 | 316 |
| 2019 | 397 | 447 |
| 2020 | 448 | 477 |
| 2021 | 346 | 428 |
| 2022 | 335 | 398 |
| 2023 | 301 | 429 |
| 2024 | 311 | 408 |
| 2025 | 353 | 476 |
| 2026 | 182 | 188 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Selective deposition of gate dielectric layer of semiconductor device and the semiconductor device manufactured thereby6 Oct 2026US 12,757,424 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device including multiple spacers and method for preparing the same6 Oct 2026US 12,757,429 B2Nanya Technology Corporation
- Contact formation with staggered gate patterning6 Oct 2026US 12,757,441 B2International Business Machines Corporation
- Manufacturing method for a semiconductor structure6 Oct 2026US 12,757,466 B2Taiwan Semiconductor Manufacturing Company.Ltd
- HEMT device with field plates6 Oct 2026US 12,757,468 B2GLOBALFOUNDRIES U. S. Inc.
- Doping profile for strained source/drain region8 Oct 2026US 2026/0313975 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device8 Oct 2026US 2026/0313982 A1Samsung Electronics Co., Ltd.
- Semiconductor device structure and method for forming the same8 Oct 2026US 2026/0313987 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor structure and method for forming the same8 Oct 2026US 2026/0314008 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor structure having self-aligned insulating feature and methods for manufacturing the same8 Oct 2026US 2026/0314012 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Active programmable electronic devices for molecular biological analysis and diagnostics1,006US 5,605,662 ANanogen, Inc. · 1997
- Self aligned contact scheme568US 9,548,366 B1Taiwan Semiconductor Manufacturing Company.Ltd · 2017
- Wrap-around contact550US 9,443,769 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2016
- Method of forming self-aligned contacts and local interconnects549US 8,076,230 B2Macronix International Co., Ltd. · 2011
- Method for fabricating silicon nitride spacer structures533US 7,294,581 B2APPLIED Materials.Inc. · 2007