Semiconductor structure having self-aligned insulating feature and methods for manufacturing the same

A semiconductor structure, comprising:

• a substrate;
• a channel structure disposed on the substrate and having an uppermost surface facing away from the substrate;
• a gate structure disposed on the channel structure and including a gate electrode and a gate dielectric layer which is disposed to separate the channel structure from the gate electrode, the gate structure including an upper gate portion which is located at a level higher than a level of the uppermost surface of the channel structure;
• a gate spacer which is disposed on a sidewall of the upper gate portion;
• a source/drain feature interfacing a sidewall of the channel structure;
• a first inter-layer dielectric layer disposed over the source/drain feature;
• an insulating feature disposed over the upper gate portion, the gate spacer, and the first inter-layer dielectric layer, the insulating feature including a cap portion which is made of a dielectric material different from a dielectric material of the gate spacer, and which is disposed on the upper gate portion and extends beyond the sidewall of the upper gate portion;
• a second inter-layer dielectric layer disposed on the insulating feature opposite to the first inter-layer dielectric layer;
• and
• a conductive feature extending through the second inter-layer dielectric layer, the insulating feature, and the first inter-layer dielectric layer, so as to be connected to the source/drain feature.

A semiconductor structure, comprising:

• a substrate;
• a first channel structure and a second channel structure disposed on the substrate;
• a first gate structure and a second gate structure respectively disposed on the first channel structure and the second channel structure, the first gate structure and the second gate structure extending lengthwise in a first direction and being spaced apart from each other in the first direction, the first gate structure interfacing at least three surfaces of the first channel structure and having a first upper gate portion which is located at a level higher than an uppermost surface of the first channel structure facing away from the substrate, the second gate structure interfacing at least three surfaces of the second channel structure and having a second upper gate portion which is located at a level higher than a level of an uppermost surface of the second channel structure facing away from the substrate;
• a first gate spacer and a second gate spacer respectively disposed on a sidewall of the first upper gate portion and a sidewall of the second upper gate portion;
• a gate isolation disposed between the first gate structure and the second gate structure;
• a first source/drain feature and a second source/drain feature disposed on the substrate and respectively interfacing a sidewall of the first channel structure and a sidewall of the second channel structure;
• and
• an inter-layer dielectric layer disposed on the first source/drain feature and the second source/drain feature, the inter-layer dielectric layer being separated from the first upper gate portion and the second upper gate portion respectively by the first gate spacer and the second gate spacer;
• and
• an insulating feature disposed over the first upper gate portion and the second upper gate portion, the first gate spacer, the second gate spacer, the inter-layer dielectric layer, and the gate isolation, the insulating feature including a first portion which is made of a dielectric material different from a dielectric material of the first gate spacer and the second gate spacer, and which is disposed on the first upper gate portion and the second upper gate portion and extends in the first direction onto the gate isolation.