Semiconductor device

A method for manufacturing a semiconductor device, comprising:

• forming first to fourth patterns on a substrate, each of the first to fourth patterns extending in a first direction, the second pattern spaced apart from the first pattern in the first direction, the third pattern spaced apart from the first pattern in a second direction different from the first direction, the fourth pattern spaced apart from the third pattern in the first direction;
• forming a first plurality of nanosheets on the first pattern, a second plurality of nanosheets on the second pattern, a third plurality of nanosheets on the third pattern, and a fourth plurality of nanosheets on the fourth pattern;
• and
• forming first and second gate electrodes extending in the second direction, the first gate electrodes intersecting each of the first and third patterns, the second gate electrodes intersecting each of the second and fourth patterns, the first gate electrodes surrounding each of the first and third plurality of nanosheets, the second gate electrodes surrounding each of the second and fourth plurality of nanosheets,
• wherein a width of the first gate electrode in the first direction of a portion overlapping the first plurality of nanosheets in the first direction is smaller than a width of the first gate electrode in the first direction of a portion overlapping the third plurality of nanosheets in the first direction, and
• wherein a first pitch in the first direction between the first pattern and the second pattern is smaller than a second pitch in the first direction between the third pattern and the fourth pattern.

A method for manufacturing a semiconductor device, comprising:

• providing a substrate having an NMOS region and a PMOS region defined therein;
• forming first and second patterns on the substrate of the NMOS region, and forming third and fourth patterns on the substrate of the PMOS region, each of the first to fourth patterns extending in a first direction, the second pattern spaced apart from the first pattern in the first direction, the third pattern spaced apart from the first pattern in a second direction different from the first direction, the fourth pattern spaced apart from the third pattern in the first direction;
• forming a field insulating layer on a sidewall of each of the first to fourth patterns on the substrate;
• forming a first plurality of nanosheets on the first pattern, a second plurality of nanosheets on the second pattern, a third plurality of nanosheets on the third pattern, and a fourth plurality of nanosheets on the fourth pattern;
• and
• forming first and second gate electrodes extending in the second direction, the first gate electrodes intersecting each of the first and third patterns, the second gate electrodes intersecting each of the second and fourth patterns, the first gate electrodes surrounding each of the first and third plurality of nanosheets, the second gate electrodes surrounding each of the second and fourth plurality of nanosheets,
• wherein a width of the first gate electrode in the first direction of a portion overlapping the first plurality of nanosheets in the first direction is smaller than a width of the first gate electrode in the first direction of a portion overlapping the third plurality of nanosheets in the first direction,
• wherein a first pitch in the first direction between the first pattern and the second pattern is smaller than a second pitch in the first direction between the third pattern and the fourth pattern,
• wherein a third pitch in the first direction between the first plurality of nanosheets and the second plurality of nanosheets is smaller than a fourth pitch in the first direction between the third plurality of nanosheets and the fourth plurality of nanosheets, and
• wherein each of at least a part of the first gate electrode and at least a part of the second gate electrode is formed on the field insulating layer between the third pattern and the fourth pattern.