H10B 51/50

Ferroelectric ram [feram] devices comprising ferroelectric memory transistors: characterised by the boundary

Official title: characterised by the boundary region between the core and peripheral circuit regions

H10B51/50 (Ferroelectric ram [feram] devices comprising ferroelectric memory transistors: characterised by the boundary) appears on 88 US grants and 138 published applications in this corpus.

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Granted patents
88
Published applications
138
Assignees
20
Inventors
163
Latest grant
1 Sep 2026

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H10B 51/50: granted patents and published applications per publication year
YearGranted patentsPublished applications
201810
201924
202034
2021523
20221226
20231820
20242333
20252012
2026416

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