Non-volatile memory array with integrated memory and access transistors and method of making the same

A device structure, comprising:

• a semiconductor substrate comprising a frontside surface and a backside surface;
• a lower field effect transistor located over the frontside surface of the semiconductor substrate, and comprising a lower vertical semiconductor channel, at least one lower gate electrode and a lower gate dielectric layer located between a sidewall of the lower vertical semiconductor channel and a sidewall of the at least one lower gate electrode;
• and
• an upper field effect transistor located over the lower field effect transistor, and comprising an upper vertical semiconductor channel, at least one upper gate electrode and an upper gate dielectric layer located between a sidewall of the upper vertical semiconductor channel and a sidewall of the at least one upper gate electrode,
• wherein:
• the lower vertical semiconductor channel is electrically connected to the upper vertical semiconductor channel;
• one of the lower gate dielectric layer and the upper gate dielectric layer comprises a non-volatile memory material;
• and
• another one of the lower gate dielectric layer and the upper gate dielectric layer is free of any memory material.

A method of forming a device structure, comprising:

• forming a combination of bottom bit lines, base semiconductor rail structures, and a two-dimensional array of lower semiconductor pillars on a semiconductor substrate, wherein each row of the lower semiconductor pillars overlies and is adjoined to a respective one of the base semiconductor rail structures, and wherein each of the bottom bit lines contacts a respective one of the base semiconductor rail structures;
• forming a lower gate dielectric layer on sidewall segments of the lower semiconductor pillars;
• forming lower gate electrode lines, wherein each of the lower gate electrode lines is laterally spaced from a respective column of the lower semiconductor pillars by a lower gate dielectric layer;
• forming a two-dimensional array of upper semiconductor pillars, wherein each of the upper semiconductor pillars is formed directly on a top surface of a respective one of the lower semiconductor pillars;
• forming an upper gate dielectric layer on sidewall segments of the upper semiconductor pillars;
• forming upper gate electrode lines, wherein each of the upper gate electrode lines is laterally spaced from a respective column of the upper semiconductor pillars by an upper gate dielectric layer;
• and
• forming at least one top bit line on top surfaces of a respective row of upper semiconductor pillars.