Three-dimensional ferroelectric memory devices
AssigneeWuxi Petabyte Technologies Co., Ltd.
InventorsZhenyu Lu, Yushi Hu, Qian Tao
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Abstract
Embodiments of three-dimensional (3D) ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a 3D ferroelectric memory device includes a substrate and a plurality of ferroelectric memory cells each extending vertically above the substrate. Each of the ferroelectric memory cells includes a capacitor and a transistor electrically connected to the capacitor. The capacitor includes a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode. The transistor includes a channel structure, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor.
Claims30
A three-dimensional (3D) ferroelectric memory device, comprising:
- a substrate;
- a plurality of ferroelectric memory cells each extending vertically above the substrate and comprising:
- a capacitor comprising a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode;
- and
- a transistor electrically connected to the capacitor and comprising a channel structure electrically connected to the first electrode, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor;
- and
- a conductor layer extending laterally and in contact with the second electrode, the conductor layer having a different vertical dimension from the second electrode, wherein the second electrode is disposed laterally between the conductor layer and the ferroelectric layer.
A three-dimensional (3D) ferroelectric memory device, comprising:
- a substrate;
- a ferroelectric memory cell extending vertically above the substrate and comprising:
- a plurality of capacitors stacked vertically, each of the capacitors comprising a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode;
- and
- a transistor electrically connected to the capacitors and comprising a channel structure electrically connected to the first electrode, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor;
- and
- a conductor layer extending laterally and in contact with one of the second electrodes, the conductor layer having a different vertical dimension from the second electrode.
A three-dimensional (3D) ferroelectric memory device, comprising:
- a substrate;
- a first ferroelectric memory cell extending vertically above the substrate, the first ferroelectric memory cell comprising a first ferroelectric capacitor and a first transistor disposed above and electrically connected to the first ferroelectric capacitor, wherein the first ferroelectric capacitor comprises (i) a first electrode electrically connected to the first transistor, (ii) a second electrode, and (iii) a ferroelectric layer disposed laterally between the first electrode and the second electrode;
- a second ferroelectric memory cell extending vertically above the first ferroelectric memory cell, the second ferroelectric memory cell comprising a second transistor and a second ferroelectric capacitor disposed above and electrically connected to the second transistor, wherein the second ferroelectric capacitor comprises (i) a first electrode electrically connected to the second transistor, (ii) a second electrode, and (iii) a ferroelectric layer disposed laterally between the first electrode and the second electrode;
- a conductor layer extending laterally and in contact with the second electrode of the first ferroelectric capacitor, the conductor layer having a different vertical dimension from the second electrode of the first ferroelectric capacitor, wherein the second electrode is disposed laterally between the conductor layer and the ferroelectric layer;
- and
- a bit line disposed vertically between and electrically connected to the first transistor and the second transistor.
Dependencies are inferred from the claim text.